Metal capacitor and method of making the same including dielectric layer of different mechanical strength and dielectric constant regions
View Patent ↗A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented.
1. A method of forming a metal capacitor, comprising:
providing a dielectric layer having a first region, a second region, and a third region;
after forming the dielectric layer forming a dual damascene metal interconnection in the first region and forming a damascene capacitor electrode in the second region; and
performing a treatment on the dielectric layer in the second region to make a dielectric constant of the dielectric layer in the second region higher than a dielectric constant of the dielectric layer in the first region, wherein the treatment is performed on the second region and the third region of the dielectric layer simultaneously to improve the mechanical strength of the third region wherein each of the regions is spaced apart from the other regions.
2. The method of claim 1 , wherein the treatment comprises a UV radiation, a plasma treatment or an ion implantation.
3. The method of claim 2 , wherein the dielectric constant of the dielectric layer in the second region can be adjusted by controlling duration of the treatment, energy of the treatment or dosage of the treatment.
4. The method of claim 1 , wherein the treatment is performed after the dual damascene metal interconnection and the damascene capacitor electrode are formed.
5. The method of claim 1 , wherein the treatment is performed after a mask is formed on the first region and the second region is exposed through the mask.
6. The method of claim 1 , wherein the third region comprises a non-critical region.
7. The method of claim 1 , wherein the dual damascene metal interconnection and the damascene capacitor electrode are formed by a damascene process.
8. The method of claim 1 , wherein a cap layer is positioned on the dual damascene metal interconnection.
9. The method of claim 1 , wherein the damascene capacitor electrode and the dielectric layer in the second region constitute a metal-oxide-metal (MOM) capacitor.
10. The method of claim 6 , wherein the third region is a peripheral circuit region.
11. The method of claim 6 , wherein the third region is a logic IC region.
12. The method of claim 6 , wherein the third region is an iso-region with isolated patterns.