Storage element, storage device, signal processing circuit, and method for driving storage element
View Patent ↗A storage element capable of retaining data even after supply of power supply voltage is stopped is provided. In the storage element retaining data in synchronization with a clock signal, with the use of a capacitor and a transistor having a channel in an oxide semiconductor layer, the data can be retained even after supply of power supply voltage is stopped. Here, when the transistor is turned off while the level of the clock signal is kept constant before the supply of power supply voltage is stopped, the data can be retained accurately in the capacitor. By applying such a storage element to each of a CPU, a memory, and a peripheral control device, supply of power supply voltage can be stopped in the entire system, so that the power consumption of the entire system can be reduced.
1. A semiconductor device comprising:
a first storage element comprising:
a first inverter;
a second inverter;
a first transistor comprising a channel formation region in an oxide semiconductor layer;
a first switch;
a first input terminal; and
a first output terminal,
wherein the first input terminal is electrically connected to an input terminal of the first inverter and an output terminal of the second inverter through the first switch,
wherein the first output terminal is electrically connected to an input terminal of the second inverter and a first terminal of the first transistor,
wherein an output terminal of the first inverter is electrically connected to a second terminal of the first transistor,
wherein one of the first inverter and the second inverter is provided on a first electrical path between the first switch and the first transistor, and
wherein the other of the first inverter and the second inverter is provided on a second electrical path between the first switch and the first transistor.
2. The semiconductor device according to claim 1 ,
wherein the first storage element further comprises a first capacitor,
wherein a first electrode of the first capacitor is electrically connected to the first output terminal.
3. The semiconductor device according to claim 1 ,
wherein the first storage element further comprises a first clock terminal,
wherein a first terminal of the first switch is electrically connected to the first input terminal, and
wherein a second terminal of the first switch is electrically connected to the input terminal of the first inverter and the output terminal of the second inverter, and
wherein a first control terminal of the first switch is electrically connected to the first clock terminal.
4. The semiconductor device according to claim 1 ,
wherein the first storage element further comprises a first capacitor and a first clock terminal,
wherein a first electrode of the first capacitor is electrically connected to the first output terminal,
wherein a first terminal of the first switch is electrically connected to the first input terminal, and
wherein a second terminal of the first switch is electrically connected to the input terminal of the first inverter and the output terminal of the second inverter, and
wherein a first control terminal of the first switch is electrically connected to the first clock terminal.
5. A semiconductor device according to claim 1 , further comprising:
a second storage element comprising:
a third inverter;
a fourth inverter;
a second transistor comprising an oxide semiconductor layer;
a second input terminal; and
a second output terminal,
wherein the second input terminal is electrically connected to an input terminal of the third inverter and an output terminal of the fourth inverter,
wherein the second output terminal is electrically connected to an input terminal of the fourth inverter and a first terminal of the second transistor,
wherein an output terminal of the third inverter is electrically connected to a second terminal of the second transistor, and
wherein the first output terminal is electrically connected to the second input terminal.
6. A signal processing circuit comprising:
a CPU;
a memory; and
a peripheral control device for controlling access between the memory and the CPU,
wherein the CPU, the memory, and the peripheral control device each comprise the semiconductor device according to claim 1 .
7. A method for driving a semiconductor device, the semiconductor device comprising:
a first storage element comprising:
a first inverter;
a second inverter;
a first transistor comprising an oxide semiconductor layer;
a first switch;
a first input terminal;
a first output terminal;
a first clock terminal; and
a first control terminal,
wherein the first input terminal is electrically connected to a first terminal of the first switch,
wherein a second terminal of the first switch is electrically connected to an input terminal of the first inverter and an output terminal of the second inverter,
wherein a first control terminal of the first switch is electrically connected to the first clock terminal,
wherein the first output terminal is electrically connected to an input terminal of the second inverter and a first terminal of the first transistor,
wherein an output terminal of the first inverter is electrically connected to a second terminal of the first transistor, and
wherein a gate of the first transistor is electrically connected to the first control terminal,
the method for driving the semiconductor device comprising the steps of:
supplying a first voltage to the first clock terminal in a first period;
supplying a third voltage to the first control terminal in a second period after the first period; and
stopping supply of power supply voltage to the first storage element in a third period after the second period.
8. The method for driving the semiconductor device according to claim 7 ,
wherein the first storage element further comprises a first inversion clock terminal electrically connected to a second control terminal of the first switch,
wherein the method further comprises the steps of:
supplying a second voltage to the first inversion clock terminal in the first period; and
supplying the first voltage to the first inversion clock terminal in a fourth period after the third period.
9. The method for driving the semiconductor device according to claim 8 , further comprising the steps of:
supplying the second voltage to the first inversion clock terminal in a fifth period after the fourth period.
10. The method for driving the semiconductor device according to claim 7 , further comprising the steps of:
supplying power supply voltage to the first storage element in a sixth period after the third period;
supplying a fourth voltage to the first control terminal in a seventh period after the sixth period; and
supplying a second voltage to the first clock terminal in a eighth period after the seventh period.
11. The method for driving the semiconductor device according to claim 7 ,
wherein the first storage element further comprises a first inversion clock terminal electrically connected to a second control terminal of the first switch,
wherein the method further comprises the steps of:
supplying a second voltage to the first inversion clock terminal in the first period;
supplying the first voltage to the first inversion clock terminal in a fourth period after the third period;
supplying the second voltage to the first inversion clock terminal in a fifth period after the fourth period;
supplying power supply voltage to the first storage element in a sixth period after the fifth period;
supplying a fourth voltage to the first control terminal in a seventh period after the sixth period; and
supplying the second voltage to the first clock terminal in a eighth period after the seventh period.
12. A method for driving a semiconductor device, the semiconductor device comprising:
a first storage element comprising:
a first inverter;
a second inverter;
a first transistor comprising an oxide semiconductor layer;
a first switch;
a first input terminal;
a first output terminal;
a first inversion clock terminal; and
a first control terminal,
wherein the first input terminal is electrically connected to a first terminal of the first switch,
wherein a second terminal of the first switch is electrically connected to an input terminal of the first inverter and an output terminal of the second inverter,
wherein a first control terminal of the first switch is electrically connected to the first inversion clock terminal,
wherein the first output terminal is electrically connected to an input terminal of the second inverter and a first terminal of the first transistor,
wherein an output terminal of the first inverter is electrically connected to a second terminal of the first transistor, and
wherein a gate of the first transistor is electrically connected to the first control terminal,
the method for driving the semiconductor device comprising the steps of:
supplying a first voltage to the first inversion clock terminal in a first period;
supplying a second voltage to the first inversion clock terminal in a second period after the first period;
supplying power supply voltage to the first storage element in a third period after the second period; and
supplying a third voltage to the first control terminal in a fourth period after the third period.
13. The method for driving the semiconductor device according to claim 12 ,
wherein the first storage element further comprises a first clock terminal electrically connected to a second control terminal of the first switch,
wherein the method further comprises the steps of:
supplying the second voltage to the first clock terminal in a fifth period after the fourth period.