IP Library Granted Patent US 8,611,152
Granted Patent B2
US 8,611,152 · App. 13/343,023 · Granted Dec 17, 2013

Non-volatile multilevel memory cells

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Quick Facts
Patent No.
US 8,611,152
App. No.
13/343,023
Granted
Dec 17, 2013
Kind
B2
Abstract

The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.

Claims (42)

1. A method of programming memory cells, the method comprising:

programming a first subset of commonly coupled memory cells to one of a first number (E) of program states;

programming a second subset of the commonly coupled memory cells to one of a second number (O) of program states, wherein O is greater than E;

using a first read margin associated with the first subset of cells; and

using a different read margin associated with the second subset of cells;

wherein the first number of program states and/or the second number of program states correspond to a respective non-integer number of bits.

2. The method of claim 1 , wherein the first subset of cells is interwoven with the second subset of cells such that each memory cell of the first subset is adjacent to a memory cell of the second subset.

3. A method of programming memory cells, the method comprising:

programming a first subset of commonly coupled memory cells to one of a first number (E) of program states;

programming a second subset of the commonly coupled memory cells to one of a second number (O) of program states, wherein O is greater than E;

using a first read margin associated with the first subset of cells; and

using a different read margin associated with the second subset of cells;

wherein the first subset of cells and the second subset of cells are read together as a group; and

wherein the first number of program states and/or the second number of program states correspond to a respective non-integer number of bits.

4. A method of programming memory cells, the method comprising:

programming a first subset of commonly coupled memory cells to one of a first number (E) of program states; and

programming a second subset of the commonly coupled memory cells to one of a second number (O) of program states, wherein O is twice E;

wherein the first subset of cells is interwoven with the second subset of cells such that each memory cell of the first subset is adjacent to a memory cell of the second subset; and

wherein the first number of program states and/or the second number of program states correspond to a respective non-integer number of bits.

5. The method of claim 4 , wherein the first subset of cells and the second subset of cells are commonly coupled to a row select line.

6. A method of programming memory cells, the method comprising:

programming a first subset of commonly coupled memory cells to one of a first number (E) of program states;

programming a second subset of the commonly coupled memory cells to one of a second number (O) of program states, wherein O is greater than E; and

programming a third subset of the commonly coupled memory cells to one of a third number (E2) of program states;

wherein the first number of program states and/or the third number of program states corresponds to a respective non-integer number of bits.

7. The method of claim 6 , wherein E2 is greater than O.

8. The method of claim 6 , wherein the method includes reading the first and the third subsets of cells together as a group.

9. The method of claim 8 , wherein data stored in the first and the third subsets of cells corresponds to a page of data.

10. The method of claim 6 , wherein the method includes combining data stored by a memory cell of the first subset with data stored by an adjacent memory cell of the third subset to represent an integer number of bits.

11. The method of claim 10 , wherein the method includes combining data stored by adjacent memory cells of the second subset to represent the integer number of bits.

12. A method of programming memory cells, the method comprising:

programming a first subset of commonly coupled memory cells to one of a first number (E) of program states;

programming a second subset of the commonly coupled memory cells to one of a second number (O) of program states, wherein O is greater than E; and

programming a third subset of the commonly coupled memory cells to one of a third number (E2) of program states;

wherein the second subset is programmed prior to the third subset; and

wherein the first number of program states and/or the third number of program states correspond to a respective non-integer number of bits.

13. The method of claim 12 , wherein the first, second, and third subsets of cells are commonly coupled to a row select line.

14. The method of claim 12 , wherein the method includes programming the first subset prior to programming the second and third subsets.

15. The method of claim 12 , wherein the method includes:

using a first read margin associated with the second subset of cells; and

using a different read margin associated with the third subset of cells.

16. The method of claim 15 , wherein the first read margin is greater than the different read margin.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2012
From: ARITOME, SEIICHI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027474/0494 →