FINFET DEVICE

1 . A method for fabricating a field effect transistor device, the method comprising:

removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer;

removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer; and

forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.

2 . The method of claim 1 , wherein the removing portions of the first semiconductor layer to form the first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form the second fin disposed on the second insulator layer comprises:

depositing a hardmask layer over exposed portions of the first semiconductor layer and the second semiconductor layer;

removing portions of the hardmask layer to expose portions of the first semiconductor layer and the second semiconductor layer; and

removing exposed portions of the first semiconductor layer and the second semiconductor layer.

3 . The method of claim 2 , further comprising removing exposed portions of the hardmask layer following the removing the exposed portions of the first semiconductor layer and the second semiconductor layer.

4 . The method of claim 1 , wherein the forming the first gate stack over the portion of the first fin and forming the second gate stack over the portion of the second fin comprises:

depositing a dielectric layer over exposed portions of the first insulator layer, the first fin, the second insulator layer, and the second fin;

depositing a gate conductor layer over the dielectric layer;

patterning a mask over portions of the gate conductor layer; and

removing exposed portions of the gate conductor layer and the dielectric layer.

5 . The method of claim 4 , further comprising performing a planarization process on the gate conductor layer prior to patterning the mask over portions of the gate conductor layer.

6 . The method of claim 1 , wherein the first semiconductor layer is arranged with a first crystalline orientation, and the second semiconductor layer is arranged with a second crystalline orientation, the first crystalline orientation is dissimilar from the second crystalline orientation.

7 . The method of claim 1 , wherein the first semiconductor layer is dissimilar from the second semiconductor layer.

8 . A method for fabricating a field effect transistor device, the method comprising:

removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer;

forming a spacer on a portion of the first semiconductor layer, adjacent to the first insulator layer, and the first semiconductor layer;

growing a layer of epitaxial semiconductor material on exposed portions of the second semiconductor layer;

removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer, and removing portions of the layer of epitaxial semiconductor material and the second semiconductor layer to form a second fin disposed on the second insulator layer; and

forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.

9 . The method of claim 8 , wherein the removing portions of the first semiconductor layer to form the first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form the second fin disposed on the second insulator layer comprises:

depositing a hardmask layer over exposed portions of the first semiconductor layer and the second semiconductor layer;

removing portions of the hardmask layer to expose portions of the first semiconductor layer and the second semiconductor layer; and

removing exposed portions of the first semiconductor layer and the second semiconductor layer.

10 . The method of claim 9 , further comprising removing exposed portions of the hardmask layer following the removing the exposed portions of the first semiconductor layer and the second semiconductor layer.

11 . The method of claim 8 , wherein the forming the first gate stack over the portion of the first fin and forming the second gate stack over the portion of the second fin comprises:

depositing a dielectric layer over exposed portions of the first insulator layer, the first fin, the second insulator layer, and the second fin;

depositing a gate conductor layer over the dielectric layer;

patterning a mask over portions of the gate conductor layer; and

removing exposed portions of the gate conductor layer and the dielectric layer.

12 . The method of claim 9 , wherein the forming the first gate stack over the portion of the first fin and forming the second gate stack over the portion of the second fin comprises:

depositing a dielectric layer over exposed portions of the first insulator layer, the first fin, the second insulator layer, the second fin, and the hardmask layer;

depositing a gate conductor layer over the dielectric layer;

patterning a mask over portions of the gate conductor layer; and

removing exposed portions of the gate conductor layer and the dielectric layer.

13 . The method of claim 11 , further comprising performing a planarization process on the gate conductor layer prior to patterning the mask over portions of the gate conductor layer.

14 . The method of claim 12 , further comprising performing a planarization process on the gate conductor layer prior to patterning the mask over portions of the gate conductor layer.

15 . The method of claim 8 , further comprising:

patterning a masking material over portions of the first semiconductor layer prior to removing the portion of the first semiconductor layer and the first insulator layer; and

removing the masking material following growing the layer of epitaxial semiconductor material.

16 . A field effect transistor device comprising:

a substrate;

a first insulator layer disposed on the substrate;

a semiconductor layer disposed on the first insulator layer;

a second insulator layer disposed on the semiconductor layer;

a first finFET device disposed on the first insulator layer; and

a second finFET device disposed on the second insulator layer.

17 . The device of claim 16 , wherein the first finFet device includes a fin including a first semiconductor material and a gate portion arranged substantially perpendicular to the fin, the second finFet device includes a fin including a second semiconductor material and a gate portion arranged substantially perpendicular to the fin, and the semiconductor layer includes the first semiconductor material, wherein the fin of the first finFet device is substantially parallel to the fin of the second finFet device.

18 . The device of claim 17 , wherein the first semiconductor material is arranged with a first crystalline orientation, and the second semiconductor material is arranged with a second crystalline orientation, the first crystalline orientation is dissimilar from the second crystalline orientation.

19 . The device of claim 17 , wherein a height of the fin of the first finFet device is substantially similar to a height of the fin of the second finFet device.

20 . The device of claim 17 , wherein a height of the fin of the first finFet device is substantially dissimilar to a height of the fin of the second finFet device.