Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.
1. An electronic device comprising:
a substrate;
a source region and a drain region of a transistor disposed in the substrate;
a channel region disposed between the source region and the drain region;
a dielectric disposed above the channel region;
a gate electrode disposed upon the dielectric above the channel region, the gate electrode configured with a step above the dielectric and comprising a combination of a plurality of refractory materials, wherein the gate electrode comprises a stacked gate electrode such that a conductive etch stop material is between a bottom layer and a top layer of the gate electrode; and
a first gate spacer contacting the gate electrode and a second gate spacer contacting the gate electrode, the first gate spacer separated from the second gate spacer by the gate electrode, the first and second gate spacer with the gate electrode configured such that a stress condition in a thicker side of the step is different from a stress condition in a thinner side of the step.
2. The electronic device of claim 1 , wherein the first gate spacer has a material composition different from a material composition of the second gate spacer.
3. The electronic device of claim 2 , wherein the first gate spacer includes silicon nitride and the second gate spacer includes silicon oxide.
4. The electronic device of claim 1 , wherein the first gate spacer and the second gate spacer have the same material composition, a basis for the different stress condition of the thicker side with respect to the thinner side including the first gate spacer formed at a different time than the second gate spacer.
5. The electronic device of claim 1 , wherein the first gate spacer and the second gate spacer have the same material composition, a basis for the different stress condition of the thicker side with respect to the thinner side including the first gate spacer formed at different deposition conditions than the second gate spacer.
6. The electronic device of claim 1 , wherein the transistor includes at least a partially crystallized structure at the sidewall connected to the first gate spacer and the sidewall connected to the second gate spacer being without a crystallized structure.
7. The electronic device of claim 1 , wherein the second gate spacer includes multiple insulating materials and the first gate spacer includes a number of materials less than that of the second gate spacer.
8. The electronic device of claim 1 , wherein the second gate spacer includes silicon oxide covered by silicon nitride and the first gate spacer is essentially only silicon oxide.
9. The electronic device of claim 1 , wherein the transistor includes a protective insulator disposed on the gate electrode connecting the first gate spacer to the second gate spacer.
10. The electronic device of claim 1 , wherein the first gate spacer and/or the second gate spacer includes insulating silicon carbide.
11. The electronic device of claim 1 , wherein the gate electrode extends over the channel region to an edge of each of the source region and the drain region.
12. The electronic device of claim 1 , wherein the gate electrode comprises combinations of layers of doped polysilicon, tungsten, titanium, titanium nitride, or titanium silicide.
13. The electronic device of claim 1 , wherein the etch stop layer is titanium nitride.
14. The electronic device of claim 1 , wherein an insulating material is disposed on and contacting the thinner side of the step, the insulating material extending along the thinner side of the step such that the insulating material contacts the thicker side of the step.