Semiconductor device including plural chips stacked to each other

1. A semiconductor device comprising:

a first chip outputting a bank address signal and an active signal; and

a plurality of second chips stacked on the first chip, each of the second chips including a plurality of memory banks each selected based on the bank address signal, selected one or ones of the memory banks being brought into an active state in response to the active signal, wherein

each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state, and

the first chip activates a bank active signal when at least one of the local bank active signals is activated,

wherein each of the second chips includes a substrate and a plurality of penetration electrodes penetrating through the substrate, the penetration electrodes including a plurality of first penetration electrodes and a plurality of second penetration electrodes,

the bank address signal and the active signal are supplied from the first chip to the second chips via the first penetration electrodes, and

the local bank active signals are supplied from the second chips to the first chip via the second penetration electrodes.

2. The semiconductor device as claimed in claim 1 , wherein each of the first penetration electrodes provided on one of the second chips is short-circuited to an associated one or ones of the first penetration electrodes located at a same planar position as viewed from a stacking direction provided on other of the second chips.

3. The semiconductor device as claimed in claim 1 , wherein each of the second penetration electrodes provided on one of the second chips is not short-circuited to an associated one or ones of the second penetration electrodes located at a same planar position as viewed from a stacking direction provided on other of the second chips.

4. The semiconductor device as claimed in claim 3 , wherein each of the second penetration electrodes provided on the one of the second chips is short-circuited to an associated one or ones of the second penetration electrodes located at a different planar position as viewed from the stacking direction provided on the other of the second chips.

5. A semiconductor device comprising:

a first chip outputting a bank address signal and an active signal; and

a plurality of second chips stacked on the first chip, each of the second chips including a plurality of memory banks each selected based on the bank address signal, selected one or ones of the memory banks being brought into an active state in response to the active signal, wherein

each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state,

the first chip activates a bank active signal when at least one of the local bank active signals is activated, and

the first chip can perform a first operation mode in which all of the second chips constitute one address space, and can perform a second operation mode in which the second chips are divided into a plurality of ranks each having an independent address space.

6. The semiconductor device as claimed in claim 5 , wherein the first chip selects one of the ranks based on a chip select signal supplied from outside when the second operation mode is selected.

7. The semiconductor device as claimed in claim 5 , wherein

in the first operation mode the first chip activates the bank active signal when at least one of the local bank active signals supplied from the second chips is activated, and

in the second operation mode the first chip activates the bank active signal corresponding to each of the ranks when at least one of the local bank active signals supplied from at least one of the second chips constituting corresponding one of the ranks is activated.

8. The semiconductor device as claimed in claim 7 , wherein the first chip includes a logic circuit that changes a rank of at least one of the second chips.

9. A semiconductor device comprising:

a plurality of core chips stacked to each other, each of the core chips includes a plurality of memory banks; and

a control chip that controls the core chips, wherein

the control chip supplies a chip address signal and a bank address signal to the core chips in common in response to an active command, at least one of the core chips being selected based on the chip address signal, and at least one of the memory banks included in the selected one or ones of the core chips is brought into an active state based on the bank address signal,

each of the core chips activates a local bank active signal when at least one of the memory banks included therein is in the active state, and

wherein the control chip includes an active-signal generating circuit that receives the local bank active signals independently from the core chips, the active-signal generating circuit activating a bank active signal when at least one of the local bank active signals is activated.

10. A semiconductor device comprising:

a plurality of core chips stacked to each other, each of the core chips includes a plurality of memory banks; and

a control chip that controls the core chips, wherein

the control chip supplies a chip address signal and a bank address signal to the core chips in common in response to an active command, at least one of the core chips being selected based on the chip address signal, and at least one of the memory banks included in the selected one or ones of the core chips is brought into an active state based on the bank address signal, and

each of the core chips activates a local bank active signal when at least one of the memory banks included therein is in the active state,

wherein each of the core chips includes a plurality of first penetration electrodes penetrating through front and rear surfaces thereof, and

the local bank active signals respectively output from the core chips are transmitted to the control chip via the first penetration electrodes that are electrically independent of each other.

11. The semiconductor device as claimed in claim 10 , wherein

each of the core chips further includes a plurality of second penetration electrodes penetrating through the front and rear surfaces thereof,

the second penetration electrodes each provided on different core chips and located at a same planar position are electrically connected to each other, and

the control chip transmits the chip address signal to the core chips via the second penetration electrodes.

12. The semiconductor device as claimed in claim 10 , wherein

each of the core chips further includes a plurality of third penetration electrodes penetrating through the front and rear surfaces thereof,

the third penetration electrodes each provided on different core chips and located at a same planar position are electrically connected to each other, and

the control chip transmits the bank address signal to the core chips via the third penetration electrodes.

13. A semiconductor device comprising:

a control chip configured to output a chip address signal and a bank address signal with issuing an active command; and

first and second core chips stacked with each other, each of the first and second core chips including a plurality of memory banks, one of the first and second core chips being configured to be selected in response to the chip address signal and one of the memory banks of the one of the first and second core chips being configured to be selected in response to the bank address signal, the one of the first and second core chips being configured to generate a local bank active signal in response to the one of the memory banks therein being selected;

each of the first and second core chips further including a substrate and a first penetration electrode penetrating the substrate thereof, the first penetration electrodes of the first and second core chips being out of alignment with each other in a first direction perpendicular to the substrate and being electrically coupled to each other, the local bank active signal being supplied from the one of the first and second core chips to the control chip via the first penetration electrode of the one of the first and second core chips.

14. The semiconductor device as claimed in claim 13 , wherein the control chip is configured to output another chip address signal and another bank address signal with issuing the active command, another of the first and second core chips being configured to be selected in response to another chip address signal and another of the memory banks of another of first and second core chips being configured to be selected in response to another bank address signal, another of the first and second core chips being configured to generate another local bank active signal in response to another of the memory banks therein being selected;

each of the first and second core chips further including a second penetration electrode penetrating the substrate thereof, the second penetration electrodes of the first and second core chips being out of alignment with each other in the first direction and being electrically coupled to each other, another local bank active signal being supplied from another of the first and second core chips to the control chip via the second penetration electrode of another of the first and second core chips.

15. The semiconductor device as claimed in claim 14 , wherein the second penetration electrode of the first core chip is aligned with the first penetration electrode of the second core chip in the first direction.

16. The semiconductor device as claimed in claim 15 , wherein the first penetration electrode of the first core chip is out of alignment with the second penetration electrode of the second core chip in the first direction.

17. The semiconductor device as claimed in claim 16 , wherein each of the first and second core chips further includes a third penetration electrode penetrating the substrate thereof, the third penetration electrodes of the first and second core chips being out of alignment with each other in the first direction and being electrically coupled to each other, the first penetration electrode of the first core chip being aligned with the third penetration electrode of the second core chip.