Granted Patent B2

US 8,788,896 · App. 13/348,357 · Granted Jul 22, 2014

Inventor: Ramesh C. Tekumalla (Breinigsville, PA)

Assignee: LSI Corporation

Abstract

Claims (59)

1. A scan chain lockup latch comprising:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain;

wherein the scan chain is controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal; and

wherein the data input control circuitry is configured to maintain the data input of the latching element at a substantially constant logic value when the

scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

2. The scan chain lockup latch of claim 1 wherein the latching element comprises at least one flip-flop.

3. The scan chain lockup latch of claim 1 wherein the data input control circuitry comprises logic circuitry having a first input configured to receive the scan enable signal, a second input configured to receive a data signal, and an output coupled to the data input of the latching element.

4. The scan chain lockup latch of claim 3 wherein the logic circuitry comprises one of a two-input AND gate and a two-input OR gate.

5. The scan chain lockup latch of claim 1 wherein the data input control circuitry comprises a multiplexer having a first selectable input configured to receive a data signal, a second selectable input configured to receive a substantially constant logic value, a control input configured to receive the scan enable signal, and an output coupled to the data input of the latching element.

6. The scan chain lockup latch of claim 1 wherein the substantially constant logic value is provided by coupling the second selectable input to one of a Vdd supply line and a Vss supply line.

7. The scan chain lockup latch of claim 1 wherein the data input control circuitry comprises an inverter having an input configured to receive the scan enable signal, an output coupled to the data input of the latching element, and upper and lower supply inputs, one of the supply inputs being configured to receive a data signal and the other supply input being coupled to a supply line.

8. The scan chain lockup latch of claim 7 wherein the upper supply input is coupled to a Vdd supply line and the lower supply input is configured to receive the data signal.

9. The scan chain lockup latch of claim 7 wherein the lower supply input is coupled to a Vss supply line and the upper supply input is configured to receive the data signal.

10. An integrated circuit comprising:

scan test circuitry; and

additional circuitry subject to testing utilizing the scan test circuitry;

the scan test circuitry comprising at least one scan chain having a plurality of scan cells;

the scan test circuitry further comprising at least one lockup latch, the lockup latch being arranged within the scan chain between first and second ones of the scan cells, wherein the lockup latch comprises:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the scan chain is controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal; and

wherein the data input control circuitry is configured to maintain the data input of the latching element at a substantially constant logic value when the

scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

11. The integrated circuit of claim 10 wherein the scan chain comprises a plurality of sub-chains associated with respective distinct clock domains, and wherein the scan chain lockup latch is coupled between a final scan cell of one of the sub-chains and a first scan cell of another one of the sub-chains.

12. A processing device comprising the integrated circuit of claim 10 .

13. A method comprising:

configuring a lockup latch between first and second scan cells of a scan chain;

controlling application of data to a data input of a latching element of the lockup latch responsive to a scan enable signal; and

controlling the scan chain between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal;

wherein controlling application of data to the data input of the latching element further comprises maintaining the data input of the latching element at a substantially

constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

14. A computer program product comprising a non-transitory computer-readable storage medium having computer program code embodied therein for use in scan testing an integrated circuit, wherein the computer program code when executed in a testing system causes the testing system to perform the steps of the method of claim 13 .

15. A processing system comprising:

a processor; and

a memory coupled to the processor and configured to store information characterizing an integrated circuit design;

wherein the processing system is configured to provide scan test circuitry within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells;

the scan test circuitry further comprising at least one lockup latch, the lockup latch being arranged within the scan chain between first and second ones of the scan cells, wherein the lockup latch comprises:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the scan chain is controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal; and

wherein the data input control circuitry is configured to maintain the data input of the latching element at a substantially constant logic value when the

scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

16. A scan chain lockup latch comprising:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain; and

wherein the data input control circuitry comprises logic circuitry having a first input configured to receive the scan enable signal, a second input configured to receive a data signal, and an output coupled to the data input of the latching element.

17. A scan chain lockup latch comprising:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain; and

wherein the data input control circuitry comprises a multiplexer having a first selectable input configured to receive a data signal, a second selectable input configured to receive a substantially constant logic value, a control input configured to receive the scan enable signal, and an output coupled to the data input of the latching element.

18. A scan chain lockup latch comprising:

at least one latching element; and

data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;

wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain; and

wherein the data input control circuitry comprises an inverter having an input configured to receive the scan enable signal, an output coupled to the data input of the latching element, and upper and lower supply inputs, one of the supply inputs being configured to receive a data signal and the other supply input being coupled to a supply line.

Assignments (9)

Continuity (1)