IP Library Granted Patent US 8,994,396
Granted Patent B2
US 8,994,396 · App. 13/349,722 · Granted Mar 31, 2015

Variation-tolerant self-repairing displays

Inventors: Chih-Hsiang Ho (West Lafayette, IN); Chao Lu (West Lafayette, IN); Debabrata Mohapatra (West Lafayette, IN); Kaushik Roy (West Lafayette, IN)
Assignee: Purdue Research Foundation
G09G3/3233G09G3/3648G09G2310/08G09G2320/0233G09G2320/0285G09G2330/08G09G2330/10G09G2330/12
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Quick Facts
Patent No.
US 8,994,396
App. No.
13/349,722
Granted
Mar 31, 2015
Kind
B2
Abstract

Illustrative embodiments of systems and methods for variation-tolerant, self-repairing displays are disclosed. In one illustrative embodiment, a display panel may include one or more defective pixels and a compensation circuit may be configured to extend a charging time of each of the one or more defective pixels. In another illustrative embodiment, a method may include detecting one or more defective pixels in a pixel array and extending a charging time of each of the one or more defective pixels.

Claims (15)

1. Apparatus, comprising:

a display panel including one or more defective pixels; and

a compensation circuit configured to extend a charging time of each of the one or more defective pixels, wherein the compensation circuit comprises a clock signal generator configured to apply a basic clock signal to at least some pixels of the display panel and to apply an extended clock signal to each of the one or more defective pixels.

2. The apparatus of claim 1 , wherein the one or more defective pixels comprise one or more pixels that each have a drivability below a predetermined threshold.

3. The apparatus of claim 1 , wherein the display panel comprises a liquid crystal display including a number of low temperature polycrystalline silicon thin film transistors.

4. The apparatus of claim 1 , wherein the display panel comprises an active-matrix organic light emitting diode display including a number of low temperature polycrystalline silicon thin film transistors.

5. The apparatus of claim 1 , wherein the compensation circuit comprises a detector configured to determine a location of each of the one or more defective pixels.

6. The apparatus of claim 5 , wherein the detector comprises a plurality of comparators, each of the plurality of comparators being electrically coupled to a reference voltage and to a data line of the display panel.

7. The apparatus of claim 5 , wherein the compensation circuit further comprises a memory unit configured to store the location of each of the one or more defective pixels.

8. The apparatus of claim 1 , wherein the extended clock signal comprises multiple periods of the basic clock signal.

9. The apparatus of claim 1 , wherein the clock signal generator comprises a clock selector configured to select a frequency of the basic clock signal in response to a total number of defective pixels in the display panel.

10. Apparatus comprising:

a display panel including a plurality of pixel rows;

a compensation circuit configured to detect whether each of the plurality of pixel rows includes one or more defective pixels, to apply a basic clock signal to each of the plurality of pixel rows that does not include one or more defective pixels, and to apply an extended clock signal to each of the plurality of pixel rows that includes one or more defective pixels.

11. The apparatus of claim 10 , wherein the extended clock signal comprises multiple periods of the basic clock signal.

Assignments (2)
CONFIRMATORY LICENSE Recorded May 10, 2012
From: PURDUE UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 028185/0544 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2012
From: HO, CHIH-HSIANG; LU, CHAO; MOHAPATRA, DEBABRATA; ROY, KAUSHIK
To: PURDUE RESEARCH FOUNDATION
Reel/Frame 027639/0596 →
Continuity (2)
Provisional Application 61433103 · Jan 14, 2011
Related Publication 20120182518A1 · Jul 19, 2012