IP Library Granted Patent US 8,971,123
Granted Patent B2
US 8,971,123 · App. 13/350,275 · Granted Mar 3, 2015

Memory system temperature calibration

Inventors: Gilad Marko (Be'er Sheba, IL); Shai Tubul (Be'er Sheba, IL); Alex Mostovoy (Be'er Sheba, IL)
Assignee: SanDisk IL Ltd
G11C16/26G11C11/40626G11C11/06007
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Quick Facts
Patent No.
US 8,971,123
App. No.
13/350,275
Granted
Mar 3, 2015
Kind
B2
Abstract

A nonvolatile memory system includes a memory controller chip with at least one temperature sensor that is individually calibrated, at a single temperature, after the nonvolatile memory system is assembled, so that the calibration data is stored outside the memory controller chip, in a nonvolatile memory chip, thus obviating the need for components to store calibration data in the memory controller chip.

Claims (37)

1. A method of calibrating a temperature sensor in a memory controller chip, in a multi-chip memory system, comprising:

assembling the multi-chip memory system, including connecting the memory controller chip to at least one nonvolatile memory chip;

subsequently, measuring an output of the temperature sensor at a first temperature and storing a result of the measuring in the nonvolatile memory chip;

subsequently, measuring an output of the temperature sensor at a second temperature that is different to the first temperature; and

calculating the second temperature from:

(a) the output of the temperature sensor at the second temperature;

(b) the stored result of the measuring at the first temperature; and

(c) a relationship between temperature and sensor output over a temperature range of interest of temperature sensors of a genus that includes the temperature sensor.

2. The method of claim 1 wherein the multi-chip memory system is embodied in a flash memory card, solid-state drive, or USB drive.

3. The method of claim 1 wherein the multi-chip memory system is embodied in an embedded memory system.

4. The method of claim 1 wherein the nonvolatile memory chip is a flash memory chip.

5. The method of claim 1 wherein the relationship is a slope of a straight-line relationship between temperature and sensor output over the temperature range of interest.

6. The method of claim 5 wherein the slope is obtained prior to the assembling of the multi-chip memory system.

7. The method of claim 1 wherein no temperature calibration is performed for the temperature sensor prior to the assembling.

8. The method of claim 1 wherein the measuring the output of the temperature sensor at the first temperature and storing the result of the measuring are performed in a factory prior to sale to an end user.

9. The method of claim 1 wherein the measuring the output of the temperature sensor at the first temperature provides temperature calibration for the memory controller chip without any other measuring of the output of the temperature sensor at another temperature.

10. A multi-chip nonvolatile memory system comprising:

a nonvolatile memory chip that contains a plurality of nonvolatile memory cells;

a memory controller chip that is connected to the nonvolatile memory chip;

a temperature sensor, in the memory controller chip, providing an output that is dependent on temperature; and

a temperature reading circuit connected to the output of the temperature sensor, in the memory controller chip, the temperature reading circuit calculating a temperature measurement from the output of the temperature sensor according to an offset that is stored in the nonvolatile memory chip, the offset derived from the output of the temperature sensor at a calibration temperature during calibration of the multi-chip nonvolatile memory system, and from a relationship between temperature and sensor output over a temperature range of interest of temperature sensors of a genus that includes the temperature sensor.

11. The multi-chip nonvolatile memory system of claim 10 wherein there are no e-fuses in the memory controller chip.

12. The multi-chip nonvolatile memory system of claim 10 further comprising a physical interface for connecting to a host system.

13. The multi-chip nonvolatile memory system of claim 12 wherein the physical interface is a USB interface, or memory card interface.

14. The multi-chip nonvolatile memory system of claim 12 wherein the physical interface is a Ball Grid Array (BGA) interface.

15. A method of providing on-chip calibrated temperature measurement for a temperature sensor in a memory controller chip of a multi-chip flash memory system, comprising:

obtaining a relationship between temperature and sensor output over a temperature range of interest of temperature sensors of a genus that includes the temperature sensor;

assembling the multi-chip flash memory system, including connecting the memory controller chip to a flash memory chip;

subsequently, measuring an output of the temperature sensor at a first temperature and storing a result of the measuring in the flash memory chip;

subsequently, measuring an output of the temperature sensor at a second temperature that is different to the first temperature;

calculating the second temperature from:

(d) the output of the temperature sensor at the second temperature;

(e) the stored result of the measuring at the first temperature; and

(f) the relationship between temperature and sensor output over the temperature range of interest of temperature sensors of the genus that includes the temperature sensor;

comparing the second temperature with a threshold temperature; and

modifying the operation of the memory controller chip if the second temperature is greater than the threshold temperature.

16. The method of claim 15 wherein the threshold temperature is a temperature above which continued operation of the memory controller chip is likely to cause impairment of memory controller chip functions, or damage to the memory controller chip, and wherein the modifying the operation of the memory controller chip includes modification that reduces heat generation in the memory controller chip.

Assignments (5)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2024
From: WESTERN DIGITAL ISRAEL, LTD.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069267/0794 →
CHANGE OF NAME Recorded Aug 21, 2020
From: SANDISK IL LTD
To: WESTERN DIGITAL ISRAEL LTD
Reel/Frame 053574/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2012
From: MARKO, GILAD; TUBUL, SHAI; MOSTOVOY, ALEX
To: SANDISK IL LTD
Reel/Frame 027533/0241 →
Continuity (1)
Related Publication 20130182507A1 · Jul 18, 2013