Correlated noise canceller for high-speed ethernet receivers

1. A method of operation in an Ethernet receiver circuit comprising:

for each of a plurality of channels,

sampling an input live Ethernet data signal to generate a sampled signal having a sampled correlated noise component caused by an interfering signal, and a sampled data component, the sampled correlated noise component being correlated to a previously sampled correlated noise component;

equalizing the sampled signal to generate an equalized signal;

summing, at a summer, the equalized signal with compensation signals from respective near-end crosstalk (NEXT) and far-end crosstalk (FEXT) filters to generate a summed signal;

feeding the summed signal as an input to a slicer circuit;

slicing the summed signal with the slicer circuit;

determining a slicer error based on a difference between the summed signal and a signal produced at the output of the slicer circuit;

feeding the slicer error to a correlated noise filter;

filtering the slice error to generated a correlated noise compensation signal for feeding to the summer to cancel at least a portion of the interfering signal;

wherein the summing includes summing the equalized signal with respective correlated noise compensation signals fed from the other of the plurality of channels.

2. The method according to claim 1 wherein the filtering comprises adaptively filtering.

3. The method according to claim 1 wherein the filtering comprises:

predicting a subsequent sampled noise component based on the slicer error; and

subtracting the predicted subsequent sampled noise component from a subsequently sampled signal.

4. The method according to claim 3 wherein the subsequent sampled noise component includes evaluating a plurality of previous samples.

5. The method according to claim 4 wherein the plurality of previous samples are each weighted differently in the evaluating.

6. An Ethernet receiver circuit comprising:

a plurality of channels, each channel including

an input sampler to sample an input live Ethernet data signal having a sampled correlated noise component caused by an interfering signal, the sampled correlated noise component being correlated to a previously sampled correlated noise component;

an equalizer to equalize the sampled noise component;

a summer to sum the equalized sampled noise component with compensation signals from respective NEXT and FEXT filters and generate a summed signal;

a slicer circuit to receive the summed signal to generate a slicer error signal, the slicer error signal based on a difference between the summed signal and a signal produced at the output of the slicer circuit;

a feedback path including a correlated noise canceller coupled to the slicer circuit to receive the slicer error signal and predict a subsequently sampled noise component for summation with a subsequently received input signal to generate a correlated noise compensation signal to cancel at least a portion of the interfering signal:

wherein the summer further receives respective correlated noise compensation signals fed from the other of the plurality of channels.

7. The Ethernet receiver circuit according to claim 6 wherein the noise component is based on a sinusoidal noise source.

8. The Ethernet receiver circuit according to claim 7 wherein the sinusoidal noise source comprises radio frequency interference (RFI).

9. The Ethernet receiver circuit according to claim 6 wherein the correlated noise canceller comprises an adaptive filter.

10. The Ethernet receiver circuit according to claim 9 wherein the predicted noise component is based on one or more previous noise samples.

11. The Ethernet receiver circuit according to claim 10 wherein each noise sample is associated with a tap weighting.

12. The Ethernet receiver circuit according to claim 9 wherein the adaptive filter includes a selectable number of taps.

13. The Ethernet receiver circuit according to claim 12 wherein the adaptive filter converges on a solution based upon a leakage term-based algorithm.

14. The Ethernet receiver circuit according to claim 12 wherein the adaptive filter converges on a solution based upon a regularization-based algorithm.

15. The Ethernet receiver circuit according to claim 6 embodied as a 10GBASE-T transceiver circuit.