Chip package

1. A chip package, comprising:

a semiconductor substrate having a device region and a non-device region neighboring the device region;

a package layer disposed on the semiconductor substrate;

a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region;

a ring structure disposed overlying the semiconductor substrate and underlying the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region and not surrounding the device region; and

an auxiliary pattern comprising a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

2. The chip package as claimed in claim 1 , wherein the ring structure has two openings separated from each other.

3. The chip package as claimed in claim 1 , further comprising:

at least one second ring structure disposed overlying the semiconductor substrate and underlying the package layer, and between the spacing layer and the device region, and surrounding another portion of the non-device region.

4. The chip package as claimed in claim 1 , wherein the hollow pattern has a circular shape, semi-circular shape, elliptical shape, triangular shape, square shape, rectangular shape, polygonal shape, or combinations thereof.

5. The chip package as claimed in claim 1 , wherein the material pattern has a circular shape, semi-circular shape, elliptical shape, triangular shape, square shape, rectangular shape, polygonal shape, or combinations thereof.

6. The chip package as claimed in claim 1 , wherein the material pattern comprises a plurality of pillars separated from each other, a continuous pattern surrounding the device region, or a continuous pattern having a hollow structure.

7. The chip package as claimed in claim 6 , wherein a cavity is provided between the semiconductor substrate, the package layer, and the spacing layer, wherein the continuous pattern divides the cavity into a first chamber and a second chamber and surrounds the first chamber, and the continuous pattern has at least one channel connecting the first chamber and the second chamber.

8. The chip package as claimed in claim 7 , wherein the channel is adjacent to the package layer.

9. The chip package as claimed in claim 7 , wherein the channel is adjacent to the semiconductor substrate.

10. The chip package as claimed in claim 6 , wherein a cavity is provided between the semiconductor substrate, the package layer, and the spacing layer, wherein the continuous pattern and the ring structure divide the cavity into a first chamber surrounded by the continuous pattern, a second chamber surrounded by the ring structure, and a third chamber between any two of the continuous pattern, the ring structure and the spacing layer, and the continuous pattern has at least one first channel connecting the first chamber and the third chamber, and the ring structure has at least one second channel connecting the second chamber and the third chamber.

11. The chip package as claimed in claim 1 , wherein a cavity is provided between the semiconductor substrate, the package layer, and the spacing layer, wherein the ring structure divides the cavity into a third chamber and a fourth chamber and surrounds the third chamber, and the ring structure has at least one channel connecting the third chamber and the fourth chamber.

12. The chip package as claimed in claim 1 , wherein a pattern density of the material pattern is asymmetric with respect to the device region.

13. The chip package as claimed in claim 1 , further comprising an adhesive layer disposed between the spacing layer and the semiconductor substrate or between the spacing layer and the package layer, wherein at least a portion of the adhesive layer is filled in the hollow pattern.

14. The chip package as claimed in claim 1 , wherein the spacing layer comprises a photosensitive insulating material.

15. The chip package as claimed in claim 1 , wherein the spacing layer and the auxiliary pattern are formed of the same material.

16. The chip package as claimed in claim 1 , wherein the semiconductor substrate further comprises:

a periphery bonding pad region surrounding the device region; and

conductive pads disposed in the periphery bonding pad region.

17. The chip package as claimed in claim 16 , further comprising:

a through hole located on a surface of the semiconductor substrate and exposing the conductive pads;

an insulating layer disposed on the surface of the semiconductor substrate and extending into a sidewall of the through hole;

a conductive trace layer disposed on the insulating layer and extending into a bottom of the through hole to electrically connect to the conductive pads;

a passivation layer covering the conductive trace layer and the insulating layer and having an opening exposing the conductive trace layer; and

a conductive bump disposed in the opening of the passivation layer and electrically connecting to the conductive trace layer.

18. The chip package as claimed in claim 1 , wherein the material pattern comprises at least one bar pattern across a region surrounded by the spacing layer.

19. The chip package as claimed in claim 1 , wherein the material pattern comprises a plurality of pillars aligned along a line across a region surrounded by the spacing layer.

20. The chip package as claimed in claim 1 , wherein the ring structure has a circular shape, semi-circular shape, elliptical shape, triangular shape, square shape, rectangular shape, polygonal shape, or combinations thereof.