Using a bit specific reference level to read a memory
View Patent ↗A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
1. A memory comprising:
an array of cells; and
a sense amplifier, coupled to said array of cells, to sense a state of a selected cell on an addressed line of cells using two different currents on the addressed line of cells to produce two different reference levels;
wherein said memory is a phase change memory,
wherein said array of cells includes addressed lines including a reference generator coupled to an addressed line of a cell to be sensed, and
wherein said sense amplifier compares a reference voltage generated before a read current to the addressed line of the cell to be sensed is reduced, to a voltage generated on the addressed line of the cell to be sensed after the read current is reduced.
2. The memory of claim 1 wherein said reference generator generates the reference voltage for said sense amplifier, said reference generator to change the level of a signal from said addressed line.
3. The memory of claim 2 wherein said reference generator stores a reference level from said addressed line.
4. The memory of claim 3 wherein said reference generator holds and outputs the reference level for comparison after a time delay.
5. The memory of claim 4 wherein the reference level is stored at a read current that is different from the read current used to generate a comparison voltage.
6. The memory of claim 1 wherein said sense amplifier senses whether the level on a selected addressed line is above or below a reference level.
7. The memory of claim 1 wherein said sense amplifier compares a level on the addressed line at two different times.
8. The memory of claim 7 wherein said sense amplifier to compare levels after reducing the read current on the addressed line.
9. The memory of claim 1 wherein a higher reference voltage is utilized to sense a cell in its higher resistance state and a lower reference voltage is utilized to sense a cell in its lower resistance state.
10. A system comprising:
a processor; and
a memory, coupled to said processor, including an array of cells and a sense amplifier coupled to at least one cell to sense said one cell, said sense amplifier to sense a state of a selected cell on an addressed line of cells using two different currents on the addressed line of cells to produce two different reference levels;
wherein said memory is a phase change memory,
wherein said memory includes addressed lines coupled to said cells and a reference generator coupled to an addressed line including a cell to be sensed, and
wherein said sense amplifier compares a reference voltage generated before a read current to the addressed line of the cell to be sensed is reduced, to a voltage generated on the addressed line of the cell to be sensed after the read current is reduced.
11. The system of claim 10 wherein a higher reference voltage is utilized to sense a cell in its higher resistance state and a lower reference voltage is utilized to sense a cell in its lower resistance state.
12. The system of claim 10 wherein said reference generator stores a reference level from said addressed line.
13. The system of claim 12 wherein said reference generator to reduce the level of a signal from said addressed line.
14. The system of claim 10 including a digital camera coupled to said processor.