Advanced programming verification schemes for analog memory cells
A method for data storage includes receiving in a memory device data for storage in a group of analog memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.
1. A method for data storage, comprising:
receiving in a memory device data for storage in a group of memory cells;
storing the data in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds;
immediately following successful completion of the P&V process, detecting in the memory device a mismatch between the stored data and the received data; and
reporting an error in storage of the data responsively to the mismatch;
wherein detecting a mismatch between the stored data and the received data includes comparing a variance of a histogram of the programmed states of the stored data with a corresponding variance of a histogram of the programming states of the received data.
2. The method according to claim 1 , wherein detecting the mismatch comprises receiving in the memory device a command that comprises a copy of the data and instructs the memory device to read the stored data, executing the command so as to reproduce the stored data, and detecting the mismatch between the stored data and the copy of the data received in the command.
3. The method according to claim 1 , wherein receiving the data comprises buffering the received data in the memory device until after the successful completion of the P&V process, and wherein detecting the mismatch comprises identifying the mismatch between the stored data and the buffered received data.
4. The method according to claim 3 , wherein buffering the received data comprises buffering a first copy of the received data in a first buffer for use in the P&V process, and buffering a second copy of the received data in a second buffer for comparison with the stored data following the completion of the P&V process.
5. The method according to claim 1 , wherein detecting the mismatch comprises receiving in the memory device a command that instructs the memory device to read the stored data following the completion of the P&V process and specifies one or more read thresholds for reading the stored data, executing the command so as to reproduce the stored data, and detecting the mismatch between the reproduced stored data and the received data.
6. The method according to claim 1 , wherein reporting the error comprises indicating the error only when a number of bits differing between the stored data and the received data exceeds a predefined threshold.
7. The method according to claim 1 , wherein reporting the error comprises reporting a number of bits differing between the stored data and the received data.
8. Apparatus for data storage, comprising:
multiple memory cells; and
circuitry, which is configured to:
receive data for storage in a group of the memory cells;
store the data in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds;
detect, immediately following successful completion of the P&V process, a mismatch between the stored data and the received data; and
report an error in storage of the data responsively to the mismatch;
wherein to detect the mismatch between the stored data and the received data the circuitry is further configured to compare a variance of a histogram of the programmed states of the stored data with a corresponding variance of a histogram of the programming states of the received data.
9. The apparatus according to claim 8 , wherein the circuitry is configured to receive a command that comprises a copy of the data and instructs to read the stored data, to execute the command so as to reproduce the stored data, and to detect the mismatch between the stored data and the copy of the data received in the command.
10. The apparatus according to claim 8 , wherein the circuitry is configured to buffer the received data until after the successful completion of the P&V process, and to detect the mismatch between the stored data and the buffered received data.
11. The apparatus according to claim 10 , wherein the circuitry comprises first and second buffers, and is configured to buffer a first copy of the received data in the first buffer for use in the P&V process, and to buffer a second copy of the received data in a second buffer for comparison with the stored data following the completion of the P&V process.
12. The apparatus according to claim 8 , wherein the circuitry is configured to receive a command that instructs to read the stored data following the completion of the P&V process and specifies one or more read thresholds for reading the stored data, to execute the command so as to reproduce the stored data, and to detect the mismatch between the reproduced stored data and the received data.
13. The apparatus according to claim 8 , wherein the circuitry is configured to report the error only when a number of bits differing between the stored data and the received data exceeds a predefined threshold.
14. The apparatus according to claim 8 , wherein the circuitry is configured to report a number of bits differing between the stored data and the received data.