Patent Assignment
Reel/Frame 028399/0733
Assignment of Assignor's Interest
Recorded: 2012-06-19
Pages: 58
Assignor
ANOBIT TECHNOLOGIES LTD.
Executed: 2012-06-01
Assignee
APPLE INC.
1 INFINITE LOOP, CUPERTINO, CALIFORNIA, 95014
Covered Properties
(281)
Methods and apparatus for high density memory devices
Application:
60/747,106 →
High Density Memory Systems and Methods
Application:
60/806,533 →
Algorithms for programming and reading memory devices
Application:
60/821,764 →
Algorithms for increasing density and robustness of memory devices
Application:
60/822,236 →
Algorithms for Measuring and Estimating Coupling Ratios in Memory Devices
Application:
60/823,650 →
Methods for Non-Volatile Memory
Application:
60/825,913 →
Methods for Mitigating Disturb Noise in Memory Devices
Application:
60/827,067 →
Method to Combat Aging and Crosstalk in Flash Memory Devices
Application:
60/863,480 →
Reading and Programming Methods in Memory Devices
Application:
60/863,506 →
Methods for High Resolution Sampling and Feedback Codes in Memory Devices
Application:
60/863,810 →
Programming cycle for memory devices
Application:
60/866,071 →
Capacity Management in memory devices
Application:
60/866,860 →
Architecture of high density, high performance memory devices
Application:
60/867,399 →
Methods to optimize memory devices structure using a Digital Signal Processor
Application:
60/868,342 →
Method to improve memory devices testing
Application:
60/868,731 →
Application Dependent Memory Device Interface
Application:
60/870,398 →
Algorithms for Programming and reading memory devices
Application:
60/870,399 →
Usage of Bad Blocks to Increase Capacity
Application:
60/871,838 →
Memory device in which the size of the input and output pages is different than the actual capacity of a page
Application:
60/882,240 →
Method for assessing memory capacity and optimizing memory utilization based on measuring the time periods between programming operations
Application:
60/883,071 →
Method for Mitigating Errors in Memory Devices that Combines DSP and Analog Program and Verify Algorithms
Application:
60/885,024 →
Combined Capacity Management and Coding Schemes for memory devices
Application:
60/885,987 →
Combined Interference Mitigation and Disturb Mitigation with Coding Schemes for Memory Devices
Application:
60/886,102 →
Methods for Error Estimations in Memory Array
Application:
60/886,429 →
Parameter Optimization in Memory Devices
Application:
60/888,828 →
Parameter Optimization in memory devices
Application:
60/889,277 →
Back Pattern Dependency Estimation
Application:
60/891,569 →
Methods to Implement a Combined Interference Mitigation and Disturb Mitigation with Coding Schemes for Memory Devices
Application:
60/892,869 →
Methods to Calculate the Optimized Thresholds for Reading Memory Devices
Application:
60/894,290 →
Methods to Cancel Crosstalk in Memory Devices
Application:
60/894,456 →
Command Set Extension for Memory Devices
Application:
60/912,056 →
Command Set Extension for Memory Devices
Application:
60/913,281 →
Fragment Coding for Memory devices
Application:
60/917,649 →
Methods to Improve Memory Device Functionality
Application:
60/917,653 →
Combating Back Pattern Dependency and Other Distortions in Flash Memory Devices Using Re-read with Modified Read Parameters
Application:
60/938,192 →
Estimation and Calibration Methods for Memory Devices
Application:
60/939,077 →
Coding schemes for memory devices with non-uniform error rate
Application:
60/949,515 →
Methods to calculate Soft Metrics from memory device cells
Application:
60/950,884 →
Methods to calculate Soft Metrics from memory device cells
Application:
60/951,215 →
Utilization of Redundancy & Spare Bits within Memory Devices
Application:
60/954,012 →
Memory Controller with Variable Redundancy Requirements
Application:
60/954,013 →
Methods for Preventing Program Errors in Memory Devices
Application:
60/954,169 →
Method for Improving Programming Speed of Multi-Level Cell Memory Devices without Compromising Reliability
Application:
60/954,317 →
Method for Improving Programming Speed of Multi-Level Cell Memory Devices without Compromising Reliability
Application:
60/970,058 →
Method for Programming Memory Devices
Application:
60/973,453 →
Additional Methods to Incorporate Signal Processing Module on Memory Devices
Application:
60/976,436 →
Method for Reliable Programming of Flash Devices in the Presence of Temperature Variations
Application:
60/978,146 →
Method for reading soft values from a memory device
Application:
60/981,113 →
Methods for Combating Voltage Shift In Memory Devices
Application:
60/981,116 →
Methods for Combating Erase Failure In Memory Devices
Application:
60/981,117 →
Methods for Combating Voltage Shift In Memory Devices
Application:
60/982,480 →
Methods for Combating Voltage Shift In Memory Devices
Application:
60/983,272 →
Combined Coding and Program and Verify method
Application:
60/983,950 →
Programming algorithm in MLC memory devices
Application:
60/985,236 →
Optimized Packing of Variable Capacity Memory Chips in a multi-chip Product
Application:
60/987,417 →
Optimization of sampling in flash memories
Application:
60/989,129 →
Method and Apparatus for Incremental Coding in Memory Devices
Application:
60/989,812 →
Method to reduce number of read operations during erroneous event in Flash devices
Application:
60/991,245 →
Method to adjust reading thresholds
Application:
60/991,246 →
Programming Scheme for Memory Devices
Application:
61/012,424 →
Programming Scheme for Memory Devices
Application:
61/012,933 →
Method to efficiently perform random access read in Flash devices
Application:
61/013,027 →
Method to efficiently cancel interference in Flash devices
Application:
61/013,032 →
Programming Method for Multi-Plane Memory Device
Application:
61/014,048 →
Method to efficiently perform random access read in Flash devices
Application:
61/016,566 →
Methods to Improve Read Throughput in the Event of Distortion Cancellation
Application:
61/016,570 →
Memory Device with Indications to a Memory Controller
Application:
61/016,816 →
Additional Methods to Calculate the Optimized Thresholds for Reading Memory Devices
Application:
61/016,824 →
Additional Methods to Calculate the Optimized Thresholds for Reading Memory Devices
Application:
61/017,177 →
Memory Cells with Non-Uniform Programming Levels
Application:
61/022,343 →
Enhancement of Error correction code using random bit inversion
Application:
61/022,364 →
Methods to Read Soft Values from Memory Device with minimal Throughput Penalty
Application:
61/024,561 →
Using the parity check equations of an error correction code to estimate and track parameters
Application:
61/026,150 →
Fast Cycling Level Estimation
Application:
61/026,211 →
Memory Device with Integrated Memory Buffer and Logic
Application:
61/028,226 →
Open loop NVRAM programming for increasing write throughput
Application:
61/030,240 →
Method to reduce variance of FLASH cells after retention
Application:
61/030,972 →
Open loop NVRAM programming for increasing write throughput
Application:
61/031,712 →
Reading Combined Soft and Hard Information from Memory Devices
Application:
61/034,511 →
Reduced Sense time for Flash Devices
Application:
61/037,327 →
Enhancement of Error correction code using systematic bit inversions
Application:
61/037,328 →
Reducing the peak Power consumption of ECC decoders
Application:
61/043,734 →
Reducing the average Power consumption of ECC decoders
Application:
61/043,736 →
Methods for Combating Voltage Shift In Memory Devices
Application:
61/045,628 →
Method of Hybrid decoding in FLASH memories
Application:
61/052,276 →
Method of Hybrid Decoding in Flash Memories
Application:
61/053,031 →
Programming Scheme for Memory Devices
Application:
61/054,493 →
Optimized Syndrome calculation for BCH decoders
Application:
61/061,685 →
Fast Recovery from Erase Failures
Application:
61/076,647 →
Method for a memory controller to read at thresholds outside memory device boundaries
Application:
61/078,780 →
Method for efficient data recovery of multi-bit per cell memory devices during power failure
Application:
61/086,164 →
Program & Read parameters change for Memory devices
Application:
61/086,225 →
Method for efficient data recovery of multi-bit per cell memory devices during power failure
Application:
61/086,541 →
Modified Erase Verify Procedure
Application:
61/093,366 →
Method for efficient data recovery of multi-bit per cell memory devices during power failure
Application:
61/093,461 →
ECC segmentation
Application:
61/093,613 →
Peak Sample & Jump method
Application:
61/096,806 →
Power Efficient Method for Refreshing Memory
Application:
61/096,808 →
Chien Search Using Serial Multipliers
Application:
61/105,454 →
Using Low Speed Random Access Device To Protect Data
Application:
61/105,580 →
Method for combating retention errors during un-plugged storage of memory devices
Application:
61/105,819 →
Methods to Generate Scrambler Seed in memory devices
Application:
61/109,767 →
Optimized Encoder supporting multiple cyclic codes
Application:
61/114,473 →
Method for equal-division of cells among levels for improving read performance
Application:
61/115,085 →
Storing M bits/cell using an N bits/cell device, where N<M
Application:
61/115,086 →
Co-existence and cooperation between on-memory and external signal processing algorithms to combat memory cell impairments
Application:
61/119,929 →
Flash Reliable Mode
Application:
61/120,968 →
Memory Device Interface with Additional Commands
Application:
61/141,830 →
Method for overhauling SSD and non-volatile memory devices
Application:
61/141,842 →
Dynamic Over-Provisioning Algorithm that can Improve the Reliability of Memory Devices
Application:
61/141,866 →
Methods for storing M bits/cell using an N bits/cell device, where N<M
Application:
61/144,629 →
Hierarchal Storage Device Management System
Application:
61/145,562 →
Memory Device with Adjustable & Adaptive Verify Scheme
Application:
61/156,520 →
Memory Controller with External DRAM Capabilities
Application:
61/163,133 →
Memory controller with external DRAM capabilities
Application:
61/163,138 →
Bit Reversal metric for iterative decoders
Application:
61/163,146 →
Re-program operation
Application:
61/168,604 →
Method for Optimal Thresholds Estimation
Application:
61/175,030 →
Memory Device Operation by Varying Vpass
Application:
61/187,676 →
Advanced programming techniques to combat interference and disturbs
Application:
61/218,080 →
Chien Search Using Multiple basis representation
Application:
61/221,582 →
Dynamic allocation of SLC/MLC according to estimated heat distribution
Application:
61/224,897 →
Rate Compatible codes
Application:
61/229,788 →
Systems and method for curing element in memory element array
Application:
61/234,688 →
Efficient Decoding of Error Correction Codes (ECC)
Application:
61/234,699 →
Memory Device Curing
Application:
61/243,726 →
Diagnosis through Life Time and Self Healing Memory Device
Application:
61/244,500 →
Joint Programming Schemes for Memory Devices
Application:
61/244,506 →
Chien Search Latency reduction
Application:
61/248,915 →
Methods for estimating block's condition during operation time
Application:
61/251,787 →
Encoding the modulo 2 sum of different pages in a flash device in order to decrease the probability of page failures
Application:
61/251,807 →
Reduce Read thresholds sets
Application:
61/256,200 →
Interleaved ECC method for Random Access Memories
Application:
61/263,859 →
Efficient Readout Schemes for Analog Memory Cell Devices
Application:
61/264,673 →
LLR Unit Architecture
Application:
61/264,809 →
Wordline Status Issue
Application:
61/265,763 →
SSD - Read and Write performance balancing
Application:
61/286,814 →
Hibernation Storage Area Usage for Over Provisioning during Activity Time
Application:
61/293,676 →
Recovery From Memory Device Failure Using Redundancy
Application:
61/293,808 →
Method for Error Correction Using Remote Data Storage
Application:
61/293,814 →
Recipes Command and Statuses
Application:
61/294,498 →
LDPC code design for optimized performance
Application:
61/303,415 →
Reuse of host hibernation storage space by memory controller
Application:
61/324,429 →
Special areas - v1
Application:
61/326,858 →
Special read commands for Efficient interference cancellation and soft ECC decoding for memory devices
Application:
61/330,970 →
Adaptive Over-Provisioning in Memory Systems
Application:
61/334,606 →
Current Peaks Smoothing
Application:
61/357,114 →
Shaping methods for combating voltage range degradation due to shift effects in memory systems arrays
Application:
61/363,248 →
Redundant Data Storage in Multi-Die Memory Systems
Application:
61/364,406 →
Read and Write Cache in hybrid drives
Application:
61/367,894 →
Program non integer bits per cell across wordlines
Application:
61/369,667 →
Avoid selecting last punched block
Application:
61/369,719 →
Combating the Cell-to-Cell Interference to Erased Cells
Application:
61/372,913 →
Combating the Cell-to-Cell Interference to Erased Cells
Application:
61/372,921 →
Redundant Data Storage in Multi-Die Memory Systems
Application:
61/373,883 →
Soft ECC Direction
Application:
61/374,377 →
Method for fast programming of NAND memory devices in a manner that reduces voltage shifts of erased cells
Application:
61/380,233 →
NAND block Unified conditioning
Application:
61/386,633 →
Special read commands for Efficient interference cancellation and soft ECC decoding from memory devices
Application:
61/390,193 →
Differential Level Programming
Application:
61/417,218 →
Shaping Methods for Combating Voltage Range Degradation Due to Shift Effects in Memory Arrays
Application:
61/417,315 →
Use of Spare blocks for SLC cache
Application:
61/436,606 →
Verifying Program Operation
Application:
61/436,619 →
Protection again physical failure in memory devices
Application:
61/442,252 →
Incremental redundancy codes
Application:
61/447,111 →
Management Parity LBA separately partition
Application:
61/454,584 →
Storage system that exports multiple disk interface
Application:
61/454,599 →
Interference Mitigation Using Individual Word Line Erasure Operations
Application:
61/469,854 →
Recovery from read failures in NAND flash by using volatile memory
Application:
61/471,148 →
Data Storage in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell
Application:
61/475,241 →
SAS Target Performance optimizations
Application:
61/476,287 →
NAND LSB pages utilization
Application:
61/486,284 →
Sparse Programming Method
Application:
61/486,330 →
Advanced Programming Methods
Application:
61/486,341 →
Dual FTL
Application:
61/494,916 →
Cache block garbage collection
Application:
61/497,074 →
SAS Target Performance optimizations
Application:
61/528,771 →
IPR Proposals
Application:
61/534,389 →
Using dynamic mapping for die balancing in solid state drives
Application:
61/536,597 →
Optimized decoding of linear codes
Application:
61/537,144 →
Efficient Programming schemes to protect data from power failure during programming
Application:
61/557,428 →
Reuse of Host Hibernation Storage Space by Memory Controller
Patent:
8,694,814 →
Application:
12/880,101 →
Memory Management Schemes for Non-Volatile Memory Devices
Patent:
8,677,054 →
Application:
12/963,649 →
Redundant Data Storage in Multi-Die Memory Systems
Patent:
8,572,311 →
Application:
12/987,174 →
Redundant Data Storage Schemes for Multi-Die Memory Systems
Patent:
8,677,203 →
Application:
12/987,175 →
Reducing Peak Current in Memory Systems
Patent:
8,572,423 →
Application:
13/021,754 →
Estimation of Memory Cell Read Thresholds by Sampling Inside Programming Level Distribution Intervals
Patent:
8,482,978 →
Application:
13/170,202 →
Efficient Selection of Memory Blocks for Compaction
Patent:
8,856,475 →
Application:
13/171,467 →
Data Storage in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell
Patent:
8,645,794 →
Application:
13/192,495 →
Interference Mitigation Using Individual Word Line Erasure Operations
Patent:
8,493,781 →
Application:
13/192,504 →
Rejuvenation of Analog Memory Cells
Memory Device with Adaptive Capacity
Data Storage with Incremental Redundancy
Programming Schemes for Multi-Level Analog Memory Cells
Efficient Interference Cancellation in Analog Memory Cell Arrays
Efficient Data Storage in Multi-Plane Memory Devices
Decoding of Error Correction Code Using Partial Bit Inversion
Efficient Readout from Analog Memory Cells Using Data Compression
High-Performance Ecc Decoder
Patent:
8,327,242 →
Application:
12/419,304 →
Adaptive Estimation of Memory Cell Read Thresholds
Data Storage in Analog Memory Cells Using Modified Pass Voltages
Patent:
8,498,151 →
Application:
12/534,893 →
Segmented Data Storage
Patent:
8,949,684 →
Application:
12/551,583 →
Efficient Data Storage in Storage Device Arrays
Patent:
8,239,734 →
Application:
12/579,432 →
Memory Device with Internal Signap Processing Unit
Data Scrambling in Memory Devices
Patent:
8,713,330 →
Application:
12/607,078 →
Data Scrambling Schemes for Memory Devices
Patent:
8,261,159 →
Application:
12/607,085 →
Configurable Encoder for Cyclic Error Correction Codes
Patent:
8,484,541 →
Application:
12/616,151 →
Storage at M Bits/Cell Density in N Bits/Cell Analog Memory Cell Devices, M>N
Efficient Readout Schemes for Analog Memory Cell Devices
Patent:
8,397,131 →
Application:
12/649,358 →
Rejuvenation of Analog Memory Cells
Data Storage In Analog Memory Cell Arrays Having Erase Failures
Optimized Selection of Memory Chips in Multi-Chips Memory Devices
Memory System Including a Controller and Processors Associated with Memory Devices
Patent:
8,924,661 →
Application:
12/688,883 →
Selective Activation of Programming Schemes in Analog Memory Cell Arrays
Use of Host System Resources by Memory Controller
Dual Ecc Decoder
Patent:
8,429,498 →
Application:
12/728,289 →
Database of Memory Read Thresholds
Patent:
8,259,506 →
Application:
12/728,296 →
Selective Re-Programming of Analog Memory Cells
Patent:
8,238,157 →
Application:
12/758,003 →
Chien Search Using Multiple Basis Representation
Adaptive Over-Provisioning in Memory Systems
Patent:
8,479,080 →
Application:
12/822,207 →
Efficient Ldpc Codes
Patent:
8,601,352 →
Application:
12/843,029 →
Efficient Storage of Error Correction Information in Dram
Patent:
8,458,572 →
Application:
12/876,170 →
Error Correction Coding Over Multiple Memory Pages
Patent:
8,495,465 →
Application:
12/890,724 →
Cache Memory for Hybrid Disk Drives
Patent:
9,104,580 →
Application:
13/069,406 →
Read Commands for Reading Interfering Memory Cells
Patent:
8,694,853 →
Application:
13/088,361 →
Data Storage in Analog Memory Cells Across Word Lines Using a Non-Integer Number of Bits Per Cell
Patent:
8,767,459 →
Application:
13/192,501 →
Read Threshold Setting Based on Soft Readout Statistics
Patent:
8,694,854 →
Application:
13/195,852 →
Memory Device with Reduced Sense Time Readout
Memory Management for Unifying Memory Cell Conditions by Using Maximum Time Intervals
Patent:
9,021,181 →
Application:
13/231,963 →
Distortion Estimation and Cancellation in Memory Devices
Distortion Estimation and Cancellation in Memory Devices
Memory Device Readout Using Multiple Sense Times
Sparse Programming of Analog Memory Cells
Application:
13/338,335 →
Publication:
US 2012/0297116
Block Management Schemes in Hybrid Slc/Mlc Memory
Advanced Programming Verification Schemes for Analog Memory Cells
Protection Against Word Line Failure in Memory Devices
Patent:
8,949,686 →
Application:
13/371,443 →
Error Correction Codes for Incremental Redundancy
Automatic Defect Management in Memory Devices
Programming Orders for Reducing Distortion Based on Neighboring Rows
Reducing Distortion Using Joint Storage
Independent Management of Data and Parity Logical Block Addresses
Storage System Exporting Internal Storage Rules
Selective Data Storage in Lsb and Msb Pages
Redundant Storage in Non-Volatile Memory by Storing Redundancy Information in Volatile Memory
Efficient Connection Management in a Sas Target
High-Performance Sas Target
Application:
13/439,863 →
Publication:
US 2012/0265962
Enhanced Programming and Erasure Schemes for Analog Memory Cells
Programming and Erasure Schemes for Analog Memory Cells
Programming Orders for Reducing Distortion in Arrays of Multi-Level Analog Memory Cells
Efficient Readout Schemes for Analog Memory Cell Devices Using Multiple Read Threshold Sets
Patent:
8,174,857 →
Application:
12/649,360 →
Reliable Data Storage in Analog Memory Cells Subjected to Long Retention Periods
Patent:
8,169,825 →
Application:
12/551,567 →
Combined Distortion Estimation and Error Correction Coding for Memory Devices
Parameter Estimation Based on Error Correction Code Parity Check Equations
Reduction of Back Pattern Dependency Effects in Memory Devices
Automatic Defect Management in Memory Devices
Reading Memory Cells Using Multiple Thresholds
Wear Level Estimation in Analog Memory Cells
Reading Analog Memory Cells Using Built-in Multi-Threshold Commands
Estimation of Non-Linear Distortion in Memory Devices
Memory Device with Multiple-Accuracy Read Commands
Providing an Independent Compression Server Within a Network, as Well as a Method, Network Station and Dhcp Server
Command Interface for Memory Devices
Compensation for Voltage Drifts in Analog Memory Cells
Patent:
8,000,141 →
Application:
12/251,471 →
Estimation of Memory Cell Read Thresholds by Sampling Inside Programming Level Distribution Intervals
Patent:
8,000,135 →
Application:
12/558,528 →
Data Storage Using Modified Voltages
Patent:
7,995,388 →
Application:
12/534,898 →
Reading Memory Cells Using Multiple Thresholds
Memory Device with Non-Uniform Programming Levels
Patent:
7,925,936 →
Application:
12/171,797 →
Memory Power and Performance Management
Data Storage in Analog Memory Cells with Protection Against Programming Interruption
Patent:
7,924,613 →
Application:
12/497,707 →
Programming of Analog Memory Cells Using a Single Programming Pulse Per State Transition
High-Speed Programming of Memory Devices
Memory Device with Negative Thresholds
Programming Analog Memory Cells for Reduced Variance After Retention
Memory Cell Readout Using Successive Approximation
Reliable Data Storage in Analog Memory Cells in the Presence of Temperature Variations
Memory Device with Negative Thresholds
Adaptive Programming of Analog Memory Cells Using Statistical Characteristics
Reducing Programming Error in Memory Devices
Memory Device with Reduced Reading
Memory Device Programming Using Combined Shaping and Linear Spreading
Interference-Aware Assignment of Programming Levels in Analog Memory Cells
Patent:
8,595,591 →
Application:
13/176,761 →
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 7, 2007
From: SOKOLOV, DOTAN; SOMMER, NAFTALI
To: ANOBIT TECHNOLOGIES
Reel/Frame 019655/0682 →
Assignment of Assignor's Interest
Aug 19, 2007
From: SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 019713/0831 →
Assignment of Assignor's Interest
Aug 20, 2007
From: SOMMER, NAFTALI
To: ANOBIT TECHNOLOGIES
Reel/Frame 019713/0871 →
Assignment of Assignor's Interest
Aug 20, 2007
From: SHALVI, OFIR; SOKOLOV, DOTAN
To: ANOBIT TECHNOLOGIES
Reel/Frame 019715/0042 →
Assignment of Assignor's Interest
Aug 20, 2007
From: GURGI, EYAL; GOLOV, OREN
To: ANOBIT TECHNOLOGIES
Reel/Frame 019715/0442 →
Assignment of Assignor's Interest
Aug 20, 2007
From: SHALVI, OFIR; GURGI, EYAL
To: ANOBIT TECHNOLOGIES
Reel/Frame 019715/0832 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SOKOLOV, DOTAN; SOMMER, NAFTALI; SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 019719/0231 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SOKOLOV, DOTAN; SEMO, GIL
To: ANOBIT TECHNOLOGIES
Reel/Frame 019719/0239 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SOKOLOV, DOTAN; SHALVI, OFIR; COHEN, ZEEV
To: ANOBIT TECHNOLOGIES
Reel/Frame 019719/0245 →
Assignment of Assignor's Interest
Aug 21, 2007
From: COHEN, ZEEV
To: ANOBIT TECHNOLOGIES
Reel/Frame 019719/0937 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SOKOLOV, DOTAN; SEMO, GIL; SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 019720/0276 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SOKOLOV, DOTAN; SOMMER, NAFTALI
To: ANOBIT TECHNOLOGIES
Reel/Frame 019721/0051 →
Assignment of Assignor's Interest
Aug 21, 2007
From: SHALVI, OFIR; COHEN, ZEEV
To: ANOBIT TECHNOLOGIES
Reel/Frame 019721/0065 →
Assignment of Assignor's Interest
Jan 21, 2008
From: SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 020390/0210 →
Assignment of Assignor's Interest
Jan 21, 2008
From: ANHOLT, MICHA
To: ANOBIT TECHNOLOGIES
Reel/Frame 020390/0230 →
Assignment of Assignor's Interest
Jan 21, 2008
From: SHALVI, OFIR; SOMMER, NAFTALI
To: ANOBIT TECHNOLOGIES
Reel/Frame 020390/0238 →
Assignment of Assignor's Interest
Jan 21, 2008
From: SOKOLOV, DOTAN; SOMMER, NAFTALI
To: ANOBIT TECHNOLOGIES
Reel/Frame 020390/0241 →
Assignment of Assignor's Interest
Jan 22, 2008
From: SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 020391/0755 →
Assignment of Assignor's Interest
Mar 5, 2008
From: SOKOLOV, DOTAN; SHALVI, OFIR
To: ANOBIT TECHNOLOGIES
Reel/Frame 020600/0254 →