Memory device distributed controller system

1. A method of operation of a distributed controller system in a non-volatile memory device having a memory array comprising a plurality of memory cells, the method comprising: receiving a write command at a master controller of the non-volatile memory device, wherein the master controller is one controller of a plurality of controllers of the non-volatile memory device; determining at the master controller which of the remaining controllers of the plurality of controllers are to be activated in response to the received write command; in response to determining at the master controller to activate a data cache controller of the plurality of controllers, transmitting the received write command from the master controller to the data cache controller; in response to the write command received by the data cache controller, generating, by the data cache controller, all necessary signals to cause the data cache to accept data from a data input and to present the data to the memory array; in response to determining at the master controller to activate an analog controller of the plurality of controllers, transmitting the received write command from the master controller to the analog controller; in response to the write command received by the analog controller, determining, by the analog controller, programming voltages for programming the presented data to the memory array; and generating the programming voltages at an analog voltage generation circuit in response to signals generated by the analog controller in response to the write command received by the analog controller; wherein the master controller, the data cache controller, and the analog controller each comprise a read only instruction memory for storing instructions, an instruction decoder for decoding instructions from the instruction memory, and a logic unit for performing operations in response to decoded instructions; and

wherein the read only instruction memory stores instructions that determine timing of control signals and types of control signals that are generated to control portions of the memory array.

2. The method of claim 1 and further including receiving and interpreting commands at a command state machine of the non-volatile memory device, coupled to the master controller, and transmitting the commands to the master controller.

3. The method of claim 1 wherein the master controller controls activation of the distributed controller system by determining which of the data cache controller and the analog controller is to be activated in response to receipt of a particular command.

4. The method of claim 2 and further including the master controller generating control signals for the memory array and remaining controller circuits of the distributed controller system in response to interpreted received commands.

5. The method of claim 1 wherein the master controller circuit generates control signals to turn on select gate drain and select gate source transistors of the memory array.

6. A method for operating a distributed controller system, comprising a plurality of controllers, in a non-volatile memory device, the method comprising:

receiving a command;

interpreting the command to determine a command type;

determining at a master controller of the plurality of controllers which of the remaining controllers of the plurality of controllers are to be activated in response to the command type;

transmitting, from the master controller of the plurality of controllers, an indication of the received command type to each of the controllers of the plurality of controllers that are determined to be activated in response to the command type; and

generating, at each of the controllers of the plurality of controllers that are to be activated in response to the command type, control signals to control respective portions of the non-volatile memory device for access of a memory array of the non-volatile memory device in response to the received indication of the received command type;

wherein each of the plurality of controllers comprises a read only instruction memory for storing instructions, an instruction decoder for decoding instructions from the instruction memory, and a logic unit for performing operations in response to decoded instructions; and

wherein the read only instruction memory stores instructions that determine timing of control signals and types of control signals that are generated to control portions of the non-volatile memory device.

7. The method of claim 6 and further including the master controller generating control signals for activating circuit elements within the memory array.

8. The method of claim 6 wherein the plurality of controllers comprise the master controller, an analog controller for controlling an analog voltage generation circuit, and a data cache controller for controlling a data cache.

9. The method of claim 8 wherein the analog controller is not directly connected to the data cache controller.

10. The method of claim 6 wherein the memory device is configured in one of a NAND architecture, a NOR architecture, or an AND architecture.

11. The method of claim 6 wherein the master controller is configured to generate signals to activate the plurality of controllers.

12. The method of claim 8 and further including:

when the received command is a write command, the master controller sending a signal to the data cache controller that the write command has been received; and

the data cache controller determining that a data cache is to accept data from an input.

13. The method of claim 12 and further including:

the master controller sending a signal to the analog controller that the write command has been received; and

the analog controller determining voltages to program the accepted data to the memory device.

14. The method of claim 13 and further including:

the master controller generating additional signals to perform the memory program.

15. The method of claim 14 wherein the additional signals comprise the master controller turning on select gate drain transistors and select gate source transistors.