Memory buffer with one or more auxiliary interfaces
The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface.
1. A memory system, comprising:
a memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from a plurality of RAM chips by a first host controller;
said memory buffer further comprising at least one additional interface arranged to buffer data and/or command bytes between said first host controller and/or said RAM chips and one or more external devices coupled to said at least one additional interface;
wherein said at least one additional interface comprises at least one cross-connect interface;
said memory system further comprising:
a second memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from a plurality of RAM chips by a second host controller, said second memory buffer further comprising at least one cross-connect interface arranged to buffer data and/or command bytes between said second host controller or said RAM chips and one or more external devices coupled to said at least one additional interface;
such that data and/or command bytes can be exchanged between said first and second host controllers and/or between the RAM chips coupled to said first and second memory buffers via said cross-connect interfaces.
2. The memory system of claim 1 , wherein said at least one cross-connect interface for each of said memory buffers includes an ingress cross-connect interface for receiving data and/or command bytes from another memory buffer and an egress cross-connect interface for sending data and/or command bytes to another memory buffer.
3. The memory system of claim 2 , further comprising a switch interposed between the cross-connect interfaces of said memory buffers, said switch arranged to be operated so as to enable unidirectional or bidirectional communication between said memory buffers.
4. The memory system of claim 2 , said memory buffer arranged such that a common host is connected to a plurality of said memory buffers, each of which includes said ingress and egress cross-connect interfaces.
5. A memory system, comprising:
a memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from a plurality of RAM chips by a first host controller;
said memory buffer further comprising at least one additional interface arranged to buffer data and/or command bytes between said first host controller and/or said RAM chips and one or more external devices coupled to said at least one additional interface;
wherein said memory buffer further comprises a direct memory access (DMA) controller capable of writing data to or reading data from said RAM chips and conveying said data between the RAM chips and one or more of said memory buffer's additional interfaces;
wherein said at least one additional interface comprises at least one SATA interface, said DMA controller arranged to exchange data between said RAM chips and said at least one SATA interface.
6. A DIMM, comprising:
a plurality of random access memory (RAM) chips; and
a memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from said RAM chips by a first host controller;
said memory buffer further comprising at least one additional interface arranged to buffer data and/or command bytes between said first host controller and/or said RAM chips and one or more external devices coupled to said at least one additional interface;
wherein said at least one additional interface comprises at least one cross-connect interface;
further comprising a second DIMM, comprising:
a plurality of random access memory (RAM) chips; and
a memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from said RAM chips by a second host controller, said memory buffer further comprising at least one cross-connect interface arranged to buffer data and/or command bytes between said second host controller or said RAM chips and one or more external devices coupled to said at least one additional interface;
such that data and/or command bytes can be exchanged between said first and second host controllers and/or between the RAM chips of said first and second DIMMs via said cross-connect interfaces.
7. The DIMM of claim 6 , wherein said at least one cross-connect interface for each of said DIMMs includes an ingress cross-connect interface for receiving data and/or command bytes from another DIMM and an egress cross-connect interface for sending data and/or command bytes to another DIMM.
8. The DIMM of claim 7 , further comprising a switch interposed between the cross-connect interfaces of said DIMMs, said switch arranged to be operated so as to enable unidirectional or bidirectional communication between said DIMMs.
9. A DIMM, comprising:
a plurality of random access memory (RAM) chips; and
a memory buffer which includes an interface arranged to buffer data and/or command bytes being written to or read from said RAM chips by a first host controller;
said memory buffer further comprising at least one additional interface arranged to buffer data and/or command bytes between said first host controller and/or said RAM chips and one or more external devices coupled to said at least one additional interface;
wherein said memory buffer further comprises a direct memory access (DMA) controller capable of writing data to or reading data from said RAM chips and conveying said data between the RAM chips and one or more of said memory buffer's additional interfaces;
wherein said at least one additional interface comprises at least one SATA interface, said DMA controller arranged to exchange data between said RAM chips and said at least one SATA interface.