Pair bit line programming to improve boost voltage clamping
A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.
1. A method for programming a set of non-volatile storage elements, comprising:
(a) performing a first plurality of iterations of a programming sequence, each iteration of the first plurality of iterations includes:
(i) applying a programming pulse to the set of non-volatile storage elements while selecting a first set of pairs of adjacent non-volatile storage elements of the set for programming and inhibiting a second set of pairs of adjacent non-volatile storage elements of the set from programming, pairs of the first set are interleaved with pairs of the second set; and
(ii) subsequently performing a verify operation for the first set of pairs of adjacent non-volatile storage elements, without performing a verify operation for the second set of pairs of adjacent non-volatile storage elements; and
(b) after step (a), performing a second plurality of iterations of the programming sequence, each iteration of the second plurality of iterations includes:
(i) applying a programming pulse to the set of non-volatile storage elements while selecting the second set of pairs of adjacent non-volatile storage elements of the set for programming and inhibiting the first set of pairs of adjacent non-volatile storage elements of the set from programming; and
(ii) subsequently performing a verify operation for the second set of pairs of adjacent non-volatile storage elements, without performing a verify operation for the first set of pairs of adjacent non-volatile storage elements.
2. The method of claim 1 , wherein:
the first set of pairs is selected for programming by setting voltages of associated bit lines at a level which allows programming, and the second set of pairs is inhibited from programming by setting voltages of associated bit lines at a level which inhibits programming.
3. The method of claim 1 , wherein:
the program pulses of the first and second plurality of iterations are applied to the set of non-volatile storage elements via a word line.
4. A non-volatile storage system, comprising:
a set of non-volatile storage elements; and
at least one control circuit, the at least one control circuit, to program the set of non-volatile storage elements:
(a) performs a first plurality of iterations of a programming sequence, each iteration of the first plurality of iterations includes:
(i) application of a programming pulse to the set of non-volatile storage elements with selection of a first set of pairs of adjacent non-volatile storage elements of the set for programming and inhibition of a second set of pairs of adjacent non-volatile storage elements of the set from programming, pairs of the first set are interleaved with pairs of the second set; and
(ii) subsequent performance of a verify operation for the first set of pairs of adjacent non-volatile storage elements, without performance of a verify operation for the second set of pairs of adjacent non-volatile storage elements; and
(b) performs a second plurality of iterations of the programming sequence, each iteration of the second plurality of iterations includes:
(i) application of a programming pulse to the set of non-volatile storage elements with selection of the second set of pairs of adjacent non-volatile storage elements of the set for programming and inhibition of the first set of pairs of adjacent non-volatile storage elements of the set from programming; and
(ii) subsequent performance of a verify operation for the second set of pairs of adjacent non-volatile storage elements, without performance of a verify operation for the first set of pairs of adjacent non-volatile storage elements.
5. The non-volatile storage system of claim 4 , wherein:
the at least one control circuit, to select the first set of pairs for programming, sets voltages of associated bit lines at a level which allows programming, and to inhibit the second set of pairs from programming, sets voltages of associated bit lines at a level which inhibits programming.
6. The non-volatile storage system of claim 4 , wherein:
the at least one control circuit applies the program pulses of the first and second plurality of iterations to the set of non-volatile storage elements via a word line.