IP Library Granted Patent US 8,988,165
Granted Patent B2
US 8,988,165 · App. 13/360,119 · Granted Mar 24, 2015

Delay line phase shifter with selectable phase shift

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Quick Facts
Patent No.
US 8,988,165
App. No.
13/360,119
Granted
Mar 24, 2015
Kind
B2
Abstract

A phase shifter with selectable phase shift and comprises a switchable phase shifting element that includes a first and second signal path coupled between an input and an output and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit for controlling the switch circuit.

Claims (44)

1. A phase shifter with selectable phase shift comprising:

a switchable phase shifting element, the switchable phase shifting element further comprising;

a first signal path coupled between an input and an output and providing a first phase shift for a signal coupled through the first signal path;

a second signal path coupled between the input and the output and providing a second phase shift, differing from the first phase shift, for a signal coupled through the second signal path,

a switch circuit for selecting between the first signal path and the second signal path, the first signal path and the second signal path and the switch circuit configured to equalize first insertion loss for the first signal path and second insertion loss for the second signal path,

wherein the switchable phase shifting element further includes a reactive circuit disposed in the second signal path and configured to provide the second phase shift and a resistive loss circuit, wherein the switch circuit further comprises a switch arranged to selectively by pass the resistive loss circuit, thereby equalizing the first and second insertion loss; and

a control circuit for controlling the switch circuit.

2. The phase shifter of claim 1 wherein the switch circuit further comprises an integrated circuit switch disposed in series with the first signal path.

3. The phase shifter of claim 1 wherein the first signal path further comprises the resistive loss circuit and where the switch circuit further comprises an integrated circuit switch disposed in series with the first signal path, such that when the integrated circuit switch is activated thus selecting the first signal path, the resistive loss circuit is configured to equalize the first insertion loss and the second insertion loss expected when the second signal path is selected.

4. The phase shifter of claim 1 wherein the first signal path is configured for minimal phase shifting and wherein the second signal path is configured to provide the second phase shift to a signal coupled through the second signal path.

5. The phase shifter of claim 4 , wherein the switch circuit further comprises an integrated circuit switch arranged to by pass the resistive loss circuit when the second signal path is selected.

6. The phase shifter of claim 5 wherein the reactive circuit further comprises a first reactance series coupled at a common node to a second reactance and a shunt circuit coupled from the common node to a reference node, the shunt circuit further comprising a third reactance in series with the resistive loss circuit where the integrated circuit switch is in parallel with the resistive loss circuit.

7. The phase shifter of claim 6 wherein the first reactance and the second reactance are each an inductive reactance including at least one of a lumped inductor and a high impedance transmission line, the third reactance is a capacitive reactance including a metal insulator metal capacitor and the integrated circuit switch is a pseudo morphic high electron mobility transistor controlled by the control circuit.

8. The phase shifter of claim 1 wherein the first insertion loss for the first signal path and the second insertion loss for the second signal path are within 0.3 dB of each other.

9. The phase shifter of claim 1 further comprising:

a second switchable phase shifting element coupled in series with the switchable phase shifting element and including, in parallel, a third signal path with a third phase shift and a fourth signal path with a fourth phase shift and a second switch circuit for selecting between the third and fourth signal path, the third signal path and the fourth signal path and the second switch circuit configured to equalize third insertion loss for the third signal path and fourth insertion loss for the fourth signal path by switching in a second resistive loss circuit when the third signal path is selected.

10. The phase shifter of claim 9 wherein first and third phase shifts are minimal and the second and fourth phase shifts are different predetermined phase shifts.

11. The phase shifter of claim 9 further comprising:

a third switchable phase shifting element coupled in series with the second phase shifting element and including, in parallel, a fifth signal path with a fifth phase shift and a sixth signal path with a sixth phase shift and a third switch circuit for selecting between the fifth and sixth signal path, the fifth signal path and the sixth signal path and the third switch circuit configured to equalize fifth insertion loss for the fifth signal path and sixth insertion loss for the sixth signal path by switching in a third resistive loss circuit when the fifth signal path is selected;

wherein the second, fourth, and sixth phase shifts are different from each other.

12. The phase shifter of claim 9 wherein the first switch circuit comprises a first integrated switch in series with the first signal path and a second integrated circuit switch for switching in a first resistive loss circuit, wherein the first and second integrated circuit switch are alternatively activated and wherein the second switch circuit comprises a third integrated circuit switch in series with the third signal path and a fourth integrated circuit switch for the switching in the second resistive loss circuit, wherein the third and fourth integrated circuit switch are alternatively activated, and wherein the control circuit is configured to select at least one of minimal phase shift, a first phase shift, a second phase shift and a first plus second phase shift by activating one or more of the first, thus second, and third, thus fourth, integrated circuit switches.

13. The phase shifter of claim 1 used in a Doherty amplifier wherein the selectable phase shift is used to adjust the phase in a signal path at the input to the Doherty amplifier.

14. A phase shifter with selectable phase shift comprising:

a switchable phase shifting element, the switchable phase shifting element further comprising:

a first signal path coupled between an input and an output and providing a first phase shift for a signal coupled through the first signal path;

a second signal path coupled between the input and the output and providing a second phase shift, differing from the first phase shift, for a signal coupled through the second signal path,

a switch circuit for selecting between the first signal path and the second signal path, the first signal path and the second signal path and the switch circuit configured to equalize first insertion loss for the first signal path and second insertion loss for the second signal path,

wherein the switch circuit includes a first integrated circuit switch disposed in series with the first signal path and configured to select between the first signal path and the second signal path and a second integrated circuit switch associated with the second signal path and configured to equalize the first insertion loss and the second insertion loss; and

a control circuit for controlling the switch circuit.

15. The phase shifter of claim 14 further comprising a first and second reactance series coupled at a common node, the first and second reactance disposed in the second signal path, and further comprising a shunt circuit coupled from the common node to a reference node, wherein the shunt circuit includes a reactance series coupled to a parallel combination of a second integrated circuit switch and a resistive loss circuit.

16. A method in a phase shifter for selecting a phase shift, the method comprising:

selecting, by a switch circuit, between a first signal path and a second signal path; wherein the first and the second signal path are coupled from an input to an output, the first and second signal path having a corresponding first and second phase shift for a signal coupled through the respective first and second signal path; wherein a first insertion loss for the first signal path and a second insertion loss for the second signal path are equalized; and

providing a signal at the input,

wherein the selecting by the switch circuit includes selecting, by a first integrated circuit switch disposed in series with the first signal path, between the first signal path and the second signal path and selecting by a second integrated circuit switch associated with the second signal path a resistive loss circuit configured to equalize the first insertion loss and the second insertion loss.

17. The method of claim 16 wherein the first signal path is configured for minimal phase shifting and the second signal path is configured to provide the second phase shift to a signal coupled through the second signal path.

18. The method of claim 16 wherein the second integrated circuit switch is configured to by pass the resistive loss circuit when the second signal path is selected, the second signal path including a reactive circuit and the resistive loss circuit, the reactive circuit configured to provide the second phase shift.

19. The method of claim 16 further comprising second selecting, by a second switch circuit between a third signal path and a fourth signal path wherein the third and fourth signal path are coupled from the output to another output, the third and fourth signal path having corresponding third and fourth phase shifts for a signal coupled through the respective third and fourth signal path, wherein a third insertion loss for the third signal path and a fourth insertion loss for the fourth path are equalized, and

wherein the first and third phase shifts are minimal and the second and fourth phase shifts are predetermined phase shifts that differ each from the other.

20. A method in a phase shifter for selecting a phase shift, the method comprising:

selecting, by a switch circuit, between a first signal path and a second signal path; wherein the first and the second signal path are coupled from an input to an output, the first and second signal path having a corresponding first and second phase shift for a signal coupled through the respective first and second signal path: wherein a first insertion loss for the first signal path and a second insertion loss for the second signal path are equalized; and

providing a signal at the input,

wherein the switch circuit further includes an integrated circuit switch and the selecting further comprises controlling the integrated circuit switch to by pass a resistive loss circuit when the second signal path is selected, the second signal path including a reactive circuit and the resistive loss circuit, the reactive circuit configured to provide the second phase shift.

21. The method of claim 20 wherein the reactive circuit further comprises a first reactance and a second reactance that are series coupled at a common node and a shunt circuit coupled from the common node to a reference node, the shunt circuit further comprising a third reactance in series with the resistive loss circuit where the integrated circuit switch is in parallel with the resistive loss circuit.

22. The method of claim 21 wherein the first reactance and the second reactance are each an inductive reactance including at least one of a lumped inductor and a high impedance transmission line, the third reactance is a capacitive reactance including a metal insulator metal capacitor and the integrated circuit switch is a pseudo morphic High Electron Mobility Transistor (pHEMT).

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0455 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0521 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0476 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2012
From: STAUDINGER, JOSEPH
To: FREESCALE SEMICONDUCTOR, INC.
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