IP Library Granted Patent US 8,703,534
Granted Patent B2
US 8,703,534 · App. 13/360,796 · Granted Apr 22, 2014

Semiconductor packages and methods of packaging semiconductor devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,703,534
App. No.
13/360,796
Granted
Apr 22, 2014
Kind
B2
Abstract

A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.

Claims (30)

1. A method of forming semiconductor assemblies comprising:

providing an interposer with through interposer vias, the interposer comprises a first surface and a second surface, wherein

the through interposer vias extend from the first surface to the second surface of the interposer,

the first and second surfaces of the interposer comprise interposer contact pads thereon, the through interposer vias facilitate electrical coupling between the interposer contact pads on the first and second surfaces of the interposer, and

the second surface of the interposer comprises interposer contacts disposed thereon, the interposer contacts are configured to facilitate electrical coupling between the interposer contact pads and an external device; and

mounting a first die on a first die attach region on the first surface of the interposer, the first die comprises a first surface with first conductive contacts thereon, wherein the interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die, the first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.

2. The method in claim 1 comprises performing a reflow process to form connections between the first die and interposer.

3. The method in claim 1 comprises dispensing an underfill into a space between the first die and the first surface of the interposer.

4. The method in claim 1 comprises mounting a second die on a second die attach region on the first surface of the interposer, the second die attach region is disposed on a periphery of the first die attach region.

5. The method in claim 4 comprises performing a reflow process to form connections between the first and second dies and interposer.

6. The method in claim 4 comprises dispensing an underfill into a space between the first and second dies and the first surface of the interposer.

7. The method in claim 4 comprising forming an encapsulant on the interposer, wherein the encapsulant encapsulates the first and second dies.

8. The method in claim 1 comprises forming an encapsulant on the interposer, wherein the encapsulant encapsulates the first die.

9. The method in claim 1 comprises providing a package substrate having first and second surfaces, the first surface of the package substrate comprises first substrate contact pads, wherein the first substrate contact pads contact the interposer contacts on the second surface of the interposer.

10. The method in claim 9 comprises forming external substrate contacts on the second surface of the package substrate, the external substrate contacts serve as external package connections.

11. The method in claim 9 comprising forming an encapsulant on the package substrate, wherein the encapsulant encapsulates the first and second dies and the interposer.

12. A semiconductor assembly comprises:

an interposer with through interposer vias, the interposer comprises a first surface and a second surface, wherein

the through interposer vias extend from the first surface to the second surface of the interposer,

the first and second surfaces of the interposer comprise interposer contact pads thereon, the through interposer vias facilitate electrical coupling between the interposer contact pads on the first and second surfaces of the interposer, and

the second surface of the interposer comprises interposer contacts disposed thereon, the interposer contacts are configured to facilitate electrical coupling between the interposer contact pads and an external device; and

a first die on a first die attach region on the first surface of the interposer, the first die comprises a first surface with first conductive contacts thereon, wherein the interposer comprises material with CTE similar to that of the first die, the first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.

13. The semiconductor assembly in claim 12 comprises an underfill in a space between the first die and the first surface of the interposer.

14. The semiconductor assembly in claim 12 comprising an encapsulant disposed on the interposer, wherein the encapsulant encapsulates the first die.

15. The semiconductor assembly in claim 12 comprising a second die on a second die attach region on the first surface of the interposer, the second die attach region is disposed on a periphery of the first die attach region.

16. The semiconductor assembly in claim 15 comprising an underfill disposed in a space between the first and second dies and the first surface of the interposer.

17. The semiconductor assembly in claim 15 comprising an encapsulant disposed on the interposer, wherein the encapsulant encapsulates the first and second dies.

18. The semiconductor assembly of claim 12 comprising a package substrate having first and second surfaces, the first surface of the package substrate comprises first substrate contact pads, wherein the first substrate contact pads contact the interposer contacts on the second surface of the interposer.

19. The semiconductor assembly of claim 18 comprising external substrate contacts on the second surface of the package substrate, the external substrate contacts serve as external package connections.

20. The semiconductor assembly of claim 19 comprising an encapsulant disposed on the package substrate, wherein the encapsulant encapsulates the first and second dies and the interposer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCLUDE PATENT NUMBER 8816482 PREVIOUSLY RECORDED AT REEL: 039885 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 25, 2017
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 043979/0820 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO ADD THE ANNEX A AND THE ANNEX B WHICH WAS INADVERTENTLY LEFTOUT IN THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037959 FRAME 0822. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039885/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037959/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2012
From: TOH, CHIN HOCK; LE, KRIANGSAK SAE
To: UNITED TEST AND ASSEMBLY CENTER LTD.
Reel/Frame 027613/0466 →