IP Library Granted Patent US 8,698,664
Granted Patent B2
US 8,698,664 · App. 13/363,884 · Granted Apr 15, 2014

Continuous-time incremental analog-to-digital converter

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Quick Facts
Patent No.
US 8,698,664
App. No.
13/363,884
Granted
Apr 15, 2014
Kind
B2
Abstract

In accordance with embodiments of the present disclosure, a continuous-time incremental analog-to-digital converter (ADC) may include a plurality of resettable integrators and a feed-in gain element. Each integrator may be configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals. The plurality of integrators may include a first-stage integrator configured to receive at its input the baseband signal and a final-stage integrator configured to produce at its output a final-stage analog signal. The plurality of integrators may be arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator. The feed-in gain element may be coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators.

Claims (21)

1. A continuous-time incremental analog-to-digital converter (ADC), comprising:

a plurality of resettable integrators, each integrator configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals, the plurality of integrators comprising at least:

a first-stage integrator configured to receive at its input a baseband signal; and

a final-stage integrator configured to produce at its output a final-stage analog signal;

wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator; and

a feed-in gain element coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators, the feed-in gain element configured such that a signal transfer function of the ADC is approximately equal to a signal transfer function of a discrete-time ADC equivalent to the ADC.

2. The ADC of claim 1 , further comprising a quantizer configured to convert the final-stage analog signal to the digital output signal.

3. The ADC of claim 1 , the ADC further comprising a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC.

4. The ADC of claim 1 , the feed-in gain element comprising a resistor.

5. A wireless communication element, comprising:

a transmit path configured to convert a first digital signal into a first modulated wireless communication signal and transmit the first modulated wireless communication signal;

a receive path configured to receive a second modulated wireless communication signal and convert the second wireless communication signal into a second digital signal:

a continuous-time incremental analog-to-digital converter (ADC), the ADC comprising:

a plurality of resettable integrators, each integrator configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals, the plurality of integrators comprising at least:

a first-stage integrator configured to receive at its input a baseband signal; and

a final-stage integrator configured to produce at its output a final-stage analog signal;

wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator; and

a feed-in gain element coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators, the feed-in gain element configured such that a signal transfer function of the ADC is approximately equal to a signal transfer function of a discrete-time ADC equivalent to the ADC.

6. The wireless communication element of claim 5 , the ADC further comprising a quantizer configured to convert the final-stage analog signal to the digital output signal.

7. The wireless communication element of claim 5 , further comprising a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC.

8. The wireless communication element of claim 5 , the feed-in gain element comprising a resistor.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053062/0703 →
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053066/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2012
From: OLIAEI, OMID; RAKERS, PATRICK L.
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 027634/0740 →