Locked loop circuit with clock hold function
A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.
1. A device, comprising:
logic circuitry to select a transmit offset value when the device is to transmit data, and a receive offset value when the device is to receive data;
a phase jumping mixer to receive a set of phase vectors used to generate a clock signal having a phase offset from a reference clock signal, wherein the phase offset alternates in response to the logic circuitry between a transmit phase offset based on the transmit offset value for a first phase of the clock signal and a receive phase offset based on the receive offset value for a second phase of the clock signal; and
a transceiver clocked by the clock signal to communicate data with a remote device, the transceiver further comprising:
a receive circuit clocked by the clock signal having the receive phase offset when the logic circuitry indicates the device is receiving data from the remote device;
a transmit circuit clocked by the clock signal having the transmit phase offset when the logic circuitry indicates the device is transmitting data to the remote device.
2. The device of claim 1 , further comprising:
a storage circuit to store a transmit offset base value and a receive offset base value;
a tracking loop to generate a phase count value representing an offset between the reference clock signal and a reference phase vector in the set of phase vectors;
a summing circuit that adds the phase count value to the transmit offset base value and the receive offset base value to generate the transmit offset value and the receive offset value; and
a select circuit controlled by the logic circuitry to select between the transmit offset value and the receive offset value.
3. The device of claim 1 , further comprising:
a storage circuit to store a transmit offset base value and a receive offset base value;
a tracking loop to generate a phase count value representing an offset between the reference clock signal and a reference phase vector in the set of phase vectors;
a select circuit controlled by the logic circuitry to select between the transmit offset base value and the receive offset base value to produce a selected offset value; and
a summing circuit that adds the phase count value to the selected offset value to generate one of the transmit offset value and the receive offset value.
4. The device of claim 1 , wherein the clock signal includes a turnaround interval of time between the clock signal having the receive phase offset and the clock signal having the transmit phase offset.
5. The device of claim 1 , wherein the data is clocked at each transition of the clock signal.
6. The device of claim 1 , wherein the logic circuitry disables the transmit circuit when the device is receiving data.
7. The device of claim 6 , wherein the transmit circuit is a pull-down type circuit.
8. The device of claim 6 , wherein the transmit circuit is a push-pull driver.
9. A method, comprising:
selecting a transmit offset value when a device is to transmit data;
selecting a receive offset value when the device is to receive data;
receiving a set of phase vectors to generate a clock signal having a phase offset from a reference clock signal, wherein the phase offset is a transmit phase offset based on the transmit offset value for a first phase of the clock signal and is a receive phase offset based on the receive offset value for a second phase of the clock signal; and
clocking a transceiver with the clock signal to communicate data with a remote device, wherein the clocking comprises:
using the clock signal with the receive phase offset when receiving data from the remote device;
using the clock signal with the transmit phase offset when transmitting data to the remote device.
10. The method of claim 9 , further comprising:
storing a transmit offset base value;
storing a receive offset base value;
generating a phase count value that represents an offset between the reference clock signal and a reference phase vector in the set of phase vectors; and
adding the phase count value to one of the transmit offset base value and the receive offset base value to generate one of the transmit offset value and the receive offset value.
11. The method of claim 9 , further comprising:
storing a transmit offset base value;
storing a receive offset base value;
generating a phase count value that represents an offset between the reference clock signal and a reference phase vector in the set of phase vectors;
selecting between the transmit offset base value and the receive offset base value to produce a selected offset value; and
adding the phase count value to the selected offset value to generate one of the transmit offset value and the receive offset value.
12. The method of claim 9 , wherein the clock signal includes a turnaround interval of time between the clock signal having the receive phase offset and the clock signal having the transmit phase offset.
13. The method of claim 9 , further comprising:
clocking the data at each transition of the clock signal.
14. The method of claim 9 , further comprising:
disabling a transmit circuit within the transceiver when receiving data.
15. The method of claim 14 , wherein the transmit circuit is a pull-down type circuit.
16. The method of claim 14 , wherein the transmit circuit is a push-pull driver.
17. An integrated circuit device having an interface to transfer data to and from an external remote device, the integrated circuit device comprising:
logic circuitry to select a transmit offset value when the integrated circuit device is to output data from the interface to the external remote device, the logic circuitry to select a receive offset value when the integrated circuit device is to receive data at the interface from the external remote device, wherein logic circuitry outputs at least one control signal that indicates whether the integrated circuit device is to receive or output data to the external remote device;
a phase jumping mixer to generate a clock signal having a phase offset from a reference clock signal, wherein the phase offset alternates between being a transmit phase offset based on the transmit offset value for a first phase of the clock signal and a receive phase offset based on the receive offset value for a second phase of the clock signal;
a receive circuit to receive the data in response to the clock signal having the receive phase offset; and
a transmit circuit to output the data in response to the clock signal having the transmit phase offset.
18. The integrated circuit of claim 17 , wherein the receive circuit and transmit circuit are included in a transceiver.
19. The integrated circuit of claim 17 , wherein the receive circuit and transmit circuit are included in the interface of the integrated circuit device.
20. The integrated circuit of claim 17 , wherein the interface is to be coupled to an external signal path that transfers the data to and from the external remote device.