SEMICONDUCTOR DEVICE

1 . A semiconductor device comprising:

a first device region formed in a semiconductor substrate and defined by a device isolation region;

a first transistor of a first conduction type including a first gate electrode formed over the first device region, a first source region formed in the first device region on a first side of the first gate electrode, and a first drain region formed in the first device region on a second side of the first gate electrode;

a first pattern formed over the device isolation region on the first side of the first gate electrode in parallel with the first gate electrode;

an insulation layer formed over the semiconductor substrate, covering the first transistor and the first pattern; and

a first conductor plug buried in a first contact hole down to the first source region,

wherein the first conductor plug being electrically connected to one of a ground line and a power source line, and

the first pattern being electrically connected to the other of the ground line and the power source line.

2 . A semiconductor device according to claim 1 , which further comprises:

a second pattern formed in parallel with the first gate electrode over the device isolation region on the second side of the first gate electrode; and

a second conductor plug buried in a second contact hole down to the first drain region, wherein

the second conductor plug is electrically connected to a signal line, and

the second pattern is electrically floating.

3 . A semiconductor device according to claim 2 , which further comprises:

a second device region formed on the second side of the second pattern and defined by the device isolation region;

a second transistor of the first conduction type including a second gate electrode formed over the second device region in parallel with the second pattern, a second drain region formed in the second device region on the first side of the second gate electrode, and a second source region formed in the second device region on the second side of the second gate electrode;

a third pattern formed over the device isolation region on the second side of the second gate electrode in parallel with the second gate electrode; and

a third conductor plug buried in a third contact hole down to the second source region, wherein

the third conductor plug is electrically connected to one of the ground line and the power source line, and

the third pattern is electrically connected to the other of the ground line and the power source line.

4 . A semiconductor device according to claim 2 , further comprising:

a second device region formed on the second side of the second pattern and defined by the device isolation region;

a second transistor of a second conduction type opposite to the first conduction type including a second gate electrode formed over the second device region in parallel with the second pattern, a second drain region formed in the second device region on the first side of the second gate electrode, and a second source region formed in the second device region on the second side of the second gate electrode;

a third pattern formed over the device isolation region on the second side of the second gate electrode and formed in parallel with the second gate electrode;

a third conductor plug buried in a third contact hole down to the second source region, wherein

the third conductor plug is electrically connected to said the other of the ground line and the power source line, and

the third pattern is electrically connected to said one of the ground line and the power source line.

5 . A semiconductor device according to claim 1 , which further comprises:

a second device region formed spaced from the first device region in the longitudinal direction of the first gate electrode and defined by the device isolation region;

a second transistor of a second conduction type opposite to the first conduction type including a second gate electrode formed over the second device region, a second drain region formed in the second device region on the first side of the second gate electrode, and a second source region formed in the second device region on the second side of the second gate electrode;

a second pattern formed over the device isolation region on the second side of the second gate electrode in parallel with the second gate electrode; and

a second conductor plug buried in a second contact hole down to the second source region, wherein

the second conductor plug is electrically connected to said the other of the ground line and the power source line, and

the second pattern is electrically connected to said one of the ground line and the power source line.

6 . A semiconductor device according to claim 5 , further comprising:

a third pattern formed over the device isolation region on the second side of the first gate electrode in parallel with the first gate electrode;

a fourth pattern formed over the device isolation region on the first side of the second gate electrode in parallel with the second gate electrode;

a third conductor plug buried in a third contact hole down to the first drain region, and

a fourth conductor plug buried in a fourth contact hole down to the second drain region, wherein

the third pattern and the fourth pattern are electrically floating.

7 . A semiconductor device according to claim 6 , further comprising:

a third device region formed on the second side of the third pattern and defined by the device isolation region;

a third transistor of the first conduction type including a third gate electrode formed over the third device region in parallel with the third pattern, a third drain region formed in the third device region on the first side of the third gate electrode and a third source region formed in the third device region on the second side of the third gate electrode;

a fifth pattern formed over the device isolation region on the second side of the third gate electrode in parallel with the third gate electrode; and

a fifth conductor plug buried in a fifth contact hole down to the third source region, wherein

the fifth conductor plug is electrically connected to said one of the ground line and the power source line, and

the fifth pattern is electrically connected to said the other of the ground line and the power source line.

8 . A semiconductor device according to claim 7 , further comprising:

a fourth device region formed spaced from the third device region in the longitudinal direction of the third gate electrode and defined by the device isolation region;

a fourth transistor of the second conduction type including a fourth gate electrode formed over the fourth device region, a fourth source region formed in the fourth device region on the first side of the fourth gate electrode, and a fourth drain region formed in the fourth device region on the second side of the fourth gate electrode;

a sixth pattern formed over the device isolation region on the second side of the fourth gate electrode in parallel with the fourth gate electrode; and

a fourth conductor plug buried in a fourth contact hole down to the fourth source region, wherein

the fourth conductor plug is electrically connected to said the other of the ground line and the power source line, and

the sixth pattern is electrically floating.

9 . A semiconductor device according to claim 5 , wherein

the first gate electrode is a part of a first gate interconnection crossing the first device region and the second device region,

the second gate electrode is another part of the first gate interconnection,

the third pattern is positioned on an extended line of the second pattern, and

the fourth pattern is positioned on an extended line of the first pattern.

10 . A semiconductor device according to claim 8 , wherein

the third gate electrode is a part of a second gate interconnection crossing the third device region and the fourth device region,

the fourth gate electrode is another part of the second gate interconnection, and

the sixth pattern is positioned on an extended line of the fifth pattern.

11 . A semiconductor device according to claim 1 , wherein

the first transistor is an N-channel type transistor,

the first conductor plug is electrically connected to the ground line, and

the first pattern is electrically connected to the power source line.

12 . A semiconductor device according to claim 1 , wherein

the first transistor is a P-channel type transistor,

the first conductor plug is electrically connected to the power source line, and

the first pattern is electrically connected to the ground line.