Granted Patent B2

US 8,984,344 · App. 13/369,563 · Granted Mar 17, 2015

Abstract

Claims (39)

1. A method comprising:

storing a first address range that is used to qualify whether data trace information is to be stored at a trace buffer;

generating a first data access request by a data processor to access a first storage location; and

in response to the first storage location belonging to a memory stack of the data processor, not storing data trace information of the first data access request at the trace buffer irrespective of the first address range, otherwise,

in response to the first storage location not belonging to the memory stack of the data processor, storing data trace information of the first data access request at the trace buffer in response to determining the first storage location is within the first address range.

2. The method of claim 1 further comprising: determining that the first storage location belongs to the memory stack in response to a resource of the data processor being used that is dedicated to stack accesses.

3. The method of claim 2 , wherein the resource is a hardware resource of the data processor.

4. The method of claim 1 further comprising: determining the first storage location belongs to the memory stack in response to a register of the data processor being used that is defined to contain a stack pointer.

5. The method of claim 1 further comprising: determining the first storage location belongs to the memory stack in response to information being accessed via a dedicated port.

6. The method of claim 5 wherein the information being accessed via the dedicated port is a stack pointer.

7. The method of claim 1 further comprising determining that the first storage location belongs to the memory stack in response to determining that the data processor executing an opcode that is dedicated to accessing the memory stack.

8. The method of claim 1 further comprising: determining a process thread of the first data access request; determining whether the process thread meets a membership criteria with respect to a predefined set of process threads; and not storing data trace information of the first access request at the trace buffer irrespective of the first address range in response to determining the process thread meets the membership criteria.

9. The method of claim 1 , wherein not storing the data trace information is further responsive to determining an indicator stored at a user programmable location indicates that address range qualification based upon the first address range is irrelevant for access requests to the memory stack, otherwise, in response to determining the indicator stored at the user programmable location does not indicate that address range qualification is based upon the first address range is irrelevant for access requests to the memory stack, determining whether to store the data trace information based upon first address range.

10. The method of claim 1 further comprising:

storing a first indicator, at a first user programmable location, that indicates data trace information is not to be stored for stack accesses; and

wherein not storing data trace information of the first data access request at the trace buffer irrespective of the first address range is further in response to the first user programmable location storing the first indicator.

11. The method of claim 1 further comprising:

determining a first indicator stored at a first user programmable location;

wherein not storing data trace information of the first data access request at the trace buffer irrespective of the first address range is further in response to the first indicator being an indicator that indicates data trace information is not to be stored for access requests to the memory stack location;

storing a second address range that is used to qualify whether data trace information is to be stored at the trace buffer;

determining a second indicator stored at a second user programmable location;

in response to the first storage location being the memory stack location of the data processor and the second indicator being an indicator that indicates data trace information is not to be stored for access requests to the memory stack location, not storing data trace information of the first data access request at the trace buffer irrespective of the second address range, otherwise,

in response to the first storage location being the memory stack location of the data processor and the second indicator not being an indicator that indicates data trace information is not to be stored for access requests to the memory stack location, storing data trace information of the first data access request at the trace buffer in response to determining the first storage location is within the second address range.

12. The method of claim 1 , further comprising:

generating a second access request by a data processor to access a second storage location of the first address range; and

in response to the second storage location not belonging to the memory stack, storing data trace information of the second data access request at the trace buffer in response to determining the second storage location is within the second address range.

13. The method of claim 1 , wherein the first storage location is within the first address range.

14. A method comprising:

generating a data access request to a memory location that is within an address range of addresses for which generation of data trace messages is enabled; and

preventing a data trace message for the data access request from being stored at a trace buffer in response to determining that an address of the data access request is based upon an index value stored at a predefined storage location, wherein the predefined storage location is a general purpose register location that is identified as the predefined storage location by a user programmable value.

15. A method of claim 14 , wherein the predefined storage location is not a user selectable register location.

16. The method of claim 14 , wherein preventing the data trace message for the memory location from being stored is further responsive to a programmable indicator being asserted, otherwise, in response to the programmable indicate being negated, determining whether the data trace message is to be stored is irrespective as to whether the address of the data access request was based upon an index value stored at the predefined storage location.

17. The method of claim 14 further comprising: determining, responsive to a process thread of the data access having a predefined identifier, that the address range does not enable generation of data trace messages.

18. A processor comprising:

a first storage location to store an address range;

a second storage location to store a filtering indicator; and

filter logic comprising a comparator to compare the address range to an address of a data access request of the processor, and comprising stack access filtering logic to determine if the data access request is to a data stack of the processor, and the filter logic to prevent data trace messages from being stored at a trace buffer irrespective of a result from the comparator if it is determined the data access request is to the data stack, otherwise, if it is determined the data access is not to the data stack, the filter logic is to determine whether to store or not store the data trace message at the trace buffer based upon a result of the comparator.

19. The device of claim 18 , wherein the filter logic further comprises logic to enable the stack filtering logic responsive to the data access request belonging to a predefined thread.

20. The device of claim 19 , wherein the predefined thread is user programmable.

Assignments (31)