Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
View Patent ↗In some embodiments, a data processing system includes a processing unit, a first load/store unit LSU and a second LSU configured to operate independently of the first LSU in single and multi-thread modes. A first store buffer is coupled to the first and second LSUs, and a second store buffer is coupled to the first and second LSUs. The first store buffer is used to execute a first thread in multi-thread mode. The second store buffer is used to execute a second thread in multi-thread mode. The first and second store buffers are used when executing a single thread in single thread mode.
1. A data processing system comprising:
a processing unit including:
a first LSU (load/store unit);
a second LSU configured to operate independently of the first LSU in single and multi-thread modes;
a first store buffer coupled to the first and second LSUs; and
a second store buffer coupled to the first and second LSUs, wherein
the first store buffer is used to execute a first thread in multi-thread mode,
the second store buffer is used to execute a second thread in multi-thread mode, and
the first and second store buffers are used when executing a single thread in single thread mode.
2. The system of claim 1 wherein in single-thread mode, the first and second LSUs are configured to:
execute respective instructions concurrently if the instructions use separate L1 (Level 1) cache units.
3. The system of claim 1 further comprising:
a first load buffer coupled to the first LSU;
a second load buffer coupled to the second LSU;
logic instructions executable by the processing unit in single-thread mode to:
receive a current load instruction;
determine a physical address for the current load instruction;
determine whether there is a load buffer hit for the physical address for a load instruction that is later in chronological order than the current load instruction;
if there is a load buffer hit for the physical address,
flush a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction;
re-execute the load instruction that is later in the order than the current load instruction; and
save the physical address of the current load instruction into a corresponding one of the first and second load buffers.
4. The system of claim 1 further comprising:
logic instructions executable by the processing unit in single-thread mode to:
receive a current load instruction;
determine a physical address for the current load instruction;
determine whether there is a store buffer hit for the physical address for a store instruction that is earlier in chronological order than the current load instruction;
if there is a store buffer hit for the physical address and data for the physical address is valid, then forward the data from a store buffer corresponding to the store buffer hit to a result bus; and
if there is a store buffer hit for the physical address and data for the physical address is not valid, then set a pending indicator for the current load instruction in a corresponding one of the first and second load buffers.
5. The system of claim 1 further comprising:
a first tag array;
a second tag array;
logic instructions executable by the processing unit in single thread mode to:
receive a current load instruction;
determine a physical address for the current load instruction;
determine whether there is a store buffer hit for the physical address for a load instruction that is earlier in chronological order than the current load instruction;
if there is not a store buffer hit for the physical address and there is no tag hit in the first or second tag array for the physical address, then
send the physical address and a request associated with the current load instruction to a L2 (level 2) cache unit; and
read data from the L2 cache unit.
6. The system of claim 1 wherein the processing unit is further operable to:
a L1 cache unit;
a second L1 cache unit;
a first tag array including a first set of tags associated with the first L1 cache unit and a second set of tags associated with the second L1 cache unit;
a second tag array including another first set of tags associated with the first L1 cache unit and another second set of tags associated with the second L1 cache unit;
logic instructions executable by the processing unit in single thread mode to:
receive a current load instruction;
determine a physical address for the current instruction;
determine whether there is a store buffer hit for the physical address for a store instruction that is earlier in a chronological order of instructions than the current load instruction;
if there is not a store buffer hit for the physical address, and if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of the first and second L1 cache units, then
send the physical address to the one of the first and second L1 cache units that is not selected;
if there is a load buffer hit in one of the first and second LSUs that is not selected for the physical address for the current load instruction that is later in the order than the current load instruction, then
flush a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction; and
re-execute the load instruction that is later in the order than the current load instruction.
7. The system of claim 1 further comprising:
logic instructions executable by the processing unit in single thread mode to:
if there is not a store buffer hit for the physical address, if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of the first and second L1 cache units, then read data from the one of the first and second L1 cache units that is not selected;
if the processing unit is operating in shared cache mode, then send the physical address and a request associated with the current load instruction to a L2 cache unit; and
read data from the L2 cache unit, otherwise
if the processing unit is not operating in shared cache mode, then change a register scoreboard prediction to point to the one of the first and second L1 cache units that is not selected.
8. The system of claim 1 further comprising:
logic instructions executable by the processing unit in single thread mode to:
receive a current store instruction;
determine a physical address for the store instruction;
determine whether there is a load buffer hit for the physical address for a load instruction that is later in a chronological order of instructions than the current store instruction;
if there is a load buffer hit for the physical address, then
flush a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction; and
re-execute the load instruction that is later in the order than the current load instruction; and
save the physical address to the store buffer.
9. The system of claim 1 further comprising:
logic instructions executable by the processing unit in single thread mode to:
receive an indication to retire a store instruction from the first store buffer;
send a physical address for the store instruction to a selected cache unit;
if there is a tag hit in the first or second tag array for the physical address, the tag hit is not in the selected cache unit, and there is no shared cache line, then write data to the one of the first or second cache units that is not selected;
if the processing unit is operating in exclusive cache mode, then modify a prediction indication for a future load instruction to the one of the first or second cache units that is not selected;
send the physical address to the one of the first and second cache units that is not selected;
if there is a load buffer hit for a physical address of a load instruction received later than the instruction to be retired,
flush a pipeline of instructions in the one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction; and
re-execute the load instruction that is later in the order than the current load instruction;
if there is a tag hit in the first or second tag array for the physical address, and the tag hit is in the selected cache unit
write the data to the selected L1 cache unit;
send the physical address, data, and a request associated with the store instruction to a L2 cache unit; and
write the data to the L2 cache unit;
if there is a tag hit in the first or second tag array for the physical address, and if there is a shared cache line, write store data to both cache units or write the store data to the selected cache unit and invalidate the other cache unit.
10. A method comprising:
in a computer processing system operable in single and multi-thread modes, wherein the processing system includes a first load buffer coupled to a first LSU, a second load buffer coupled to a second LSU, and the first and second load buffers are used in single and multi-thread mode:
receiving a current load instruction in single thread mode;
determining a physical address for the current load instruction;
determining whether there is a load buffer hit in one of the first or second load buffers for the physical address for a load instruction that is later in chronological order than the current load instruction;
if there is a load buffer hit for the physical address,
flushing a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit; and
re-executing the load instruction that is later in the order than the current load instruction.
11. The method of claim 10 further comprising:
in single thread mode:
determining whether there is a store buffer hit for the physical address for a load instruction that is earlier in chronological order than the current load instruction;
if there is a store buffer hit for the physical address and data for the physical address is valid, then forwarding the data from a store buffer corresponding to the store buffer hit to a result bus; and
if there is a store buffer hit for the physical address and data for the physical address is not valid, then setting a pending indicator for the current load instruction in a corresponding one of the first and second load buffers.
12. The method of claim 10 further comprising:
in single thread mode:
determining whether there is a store buffer hit for the physical address for a load instruction that is earlier in chronological order than the current load instruction;
if there is not a store buffer hit for the physical address and there is no tag hit in the first or second tag array for the physical address, then
sending the physical address and a request associated with the current load instruction to a L2 cache unit; and
reading data from the L2 cache unit.
13. The method of claim 10 further comprising:
in single thread mode:
if there is not a store buffer hit for the physical address, and if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of the first and second L1 cache units, then
sending the physical address to one of a first and second L1 cache units that is not selected.
14. The method of claim 13 further comprising:
in single thread mode:
if there is a load buffer hit for the physical address for the current load instruction that is later in the order than the current load instruction, then
flush a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction; and
re-execute the load instruction that is later in the order than the current load instruction.
15. The method of claim 10 further comprising:
in single thread mode:
determining if there is not a store buffer hit for the physical address, and if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of first and second L1 cache units, then
reading data from the one of the first and second L1 cache units that is not selected;
if the processing unit is operating in shared cache mode, then
sending the physical address and a request associated with the current load instruction to a L2 cache unit; and
reading data from the L2 cache unit, otherwise
if the processing unit is not operating in shared cache mode, then changing a register scoreboard prediction to point to the one of the first and second L1 cache units that is not selected.
16. The method of claim 10 further comprising:
in single thread mode:
if there is a load buffer hit for the physical address, then
flushing a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetching the load instruction that is later in the order than the current load instruction;
re-executing the load instruction that is later in the order than the current load instruction; and
saving the physical address to the store buffer.
17. The method of claim 10 further comprising:
in single thread mode:
receiving an indication to retire a store instruction from a first store buffer;
sending a physical address for the store instruction to a first cache unit;
if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of the first and a second cache units, then
writing data to the one of the first or second cache units that is not selected;
if the processing unit is not operating in exclusive cache mode, then modifying a prediction indication for a future load instruction to the one of the first or second cache units that is not selected;
sending the physical address to the one of the first and second cache units that is not selected;
if there is a load buffer hit for a physical address of a load instruction received later than the instruction to be retired, then re-executing the load instruction that is later in the order than the current load instruction;
if there is a shared cache line, writing store data to the first and second cache units or write the store data to the selected cache unit and invalidate the other cache unit; and
otherwise, if there is no tag hit, sending the physical address, data, and a request associated with the current store instruction to a L2 cache unit; and writing the data to the L2 cache unit.
18. A data processing system operable in single and multi-thread modes comprising:
a processing unit;
a first L1 cache unit including a first tag array;
a second L1 cache unit including a second tag array;
a first load store unit;
a second load store unit;
a first load buffer and a first store buffer coupled to the first load store unit;
a second load buffer and a second store buffer coupled to the second load store unit;
logic instructions executable by the processing unit in single thread mode to:
receive an indication to retire a store instruction from the first store buffer;
send a physical address for the store instruction to a selected L1 cache unit;
if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in the selected L1 cache unit, then
write data to the one of the first or second cache units that is not selected;
if the processing unit is operating in exclusive cache mode, then modify a prediction indication for a future load instruction to the selected L1 cache unit;
send the physical address to the one of the first and second L1 cache units that is not selected;
if there is a load buffer hit for a physical address of a load instruction received later than the instruction to be retired, then re-execute a load instruction that was received after the instruction to be retired; and
if there is a tag hit in the first or second tag array for the physical address, and if there is a shared cache line, perform one of the group consisting of: write store data to the first and second L1 cache units, and write the store data to the selected cache unit and invalidate the other cache unit.
19. The system of claim 18 further comprising:
logic instructions executable by the processing unit in single thread mode to:
determine if there is not a store buffer hit for a physical address for an instruction, and if there is a tag hit in the first or second tag array for the physical address, and the tag hit is not in a same selected one of the first and second L1 cache units, then
read data from the one of the first and second L1 cache units that is not selected;
if the processing unit is operating in shared cache mode, then send the physical address and a request associated with the instruction to a level 2 cache unit; and
read data from the level 2 cache unit, otherwise if the processing unit is not operating in shared cache mode, then change a register scoreboard prediction to point to the one of the first and second L1 cache units that is not selected.
20. The system of claim 18 further comprising:
logic instructions executable by the processing unit in single thread mode to:
receive a current load instruction;
determine a physical address for the current load instruction;
determine whether there is a load buffer hit for the physical address for a load instruction that is later in order than the current load instruction;
if there is a load buffer hit for the physical address,
flush a pipeline of instructions in one of the first and second load buffers corresponding to the load buffer hit;
re-fetch the load instruction that is later in the order than the current load instruction;
re-execute the load instruction that is later in the order than the current load instruction; and
save the physical address of the current load instruction into the a corresponding one of the first and second load buffers.