Low voltage CMOS power on reset circuit
View Patent ↗An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.
1. An electronic circuit comprising:
a power on reset circuit coupled between a supply voltage terminal and a signal node comprising:
a voltage detector coupled to the supply voltage terminal configured to track complementary metal oxide semiconductor (CMOS) thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic, wherein the power on reset circuit further comprises:
a voltage detector comprising:
a first PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate;
a second PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate coupled to the gate of the first PMOS transistor; and
a first NMOS transistor comprising a first electrode coupled to the second electrode of the second PMOS transistor, a second electrode coupled to ground, and a gate coupled to the gates of the first and second PMOS transistors; and
a feedback path comprising:
a third PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode coupled to the gates of the first and second PMOS transistors and the first NMOS transistor, and a gate;
a fourth PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate coupled to the second electrode of the second PMOS transistor;
a second NMOS transistor comprising a first electrode coupled to the second electrode of the fourth PMOS transistor, a second electrode coupled to ground, and a gate coupled to the second electrode of the second PMOS transistor; and
an inverter coupled between the second electrode of the fourth PMOS transistor and the gate of the third PMOS transistor.
2. The electronic circuit according to claim 1 wherein the power on reset circuit further comprises:
an output driver coupled between the inverter and the signal node.
3. The electronic circuit according to claim 1 wherein:
the first PMOS transistor and the second PMOS transistor are operable as a current mirror to control and monitor current flowing to the first NMOS transistor; and
the first NMOS transistor is sufficiently larger than the second PMOS transistor to overdrive the second PMOS transistor when the supply voltage reaches a level for proper operation of CMOS logic.
4. An electronic circuit comprising:
a complementary metal oxide semiconductor (CMOS) circuit integrated on a single integrated circuit chip comprising:
a plurality of CMOS circuits; and
a power on reset circuit coupled to the plurality of CMOS circuits between a supply voltage terminal and a signal node configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic, wherein the power on reset circuit comprises NMOS and PMOS transistors and is configured to detect when the supply voltage is greater than a threshold comprising an N-type MOS threshold plus a P-type MOS threshold and, when the threshold is reached, deactivate a power on reset signal at the signal node; and
a feedback path comprising:
a third PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode coupled to the gates of the first and second PMOS transistors and the first NMOS transistor, and a gate;
a fourth PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate coupled to the second electrode of the second PMOS transistor;
a second NMOS transistor comprising a first electrode coupled to the second electrode of the fourth PMOS transistor, a second electrode coupled to ground, and a gate coupled to the second electrode of the second PMOS transistor; and
an inverter coupled between the second electrode of the fourth PMOS transistor and the gate of the third PMOS transistor.
5. The electronic circuit according to claim 4 wherein the power on reset circuit further comprises:
a voltage detector comprising:
a first PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate;
a second PMOS transistor comprising a first electrode coupled to the supply voltage, a second electrode, and a gate coupled to the gate of the first PMOS transistor; and
a first NMOS transistor comprising a first electrode coupled to the second electrode of the second PMOS transistor, a second electrode coupled to ground, and a gate coupled to the gates of the first and second PMOS transistors.
6. The electronic circuit according to claim 5 wherein:
the first PMOS transistor and the second PMOS transistor are operable as a current mirror to control and monitor current flowing to the first NMOS transistor; and
the first NMOS transistor is sufficiently larger than the second PMOS transistor to overdrive the second PMOS transistor when the supply voltage reaches a level for proper operation of CMOS logic.