Semiconductor device comprising a metal system including a separate inductor metal layer
In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.
1. An integrated circuit comprising:
a plurality of semiconductor circuit elements formed in and above a semiconductor layer formed above a substrate;
one or more first metal layers formed above said semiconductor layer, said one or more metal layers comprising metal lines having a first thickness;
a second metal layer formed above said one or more first metal layers, said second metal layer comprising power and signal routing lines having a second thickness that is greater than said first thickness; and
one or more inductor metal layers formed above said semiconductor layer, said one or more inductor metal layers comprising inductor metal lines forming one or more inductors, said inductor metal lines of at least one inductor metal layer form a first inductor and a second inductor, said inductor metal lines having a third thickness that is greater than said second thickness.
2. The integrated circuit of claim 1 , wherein each of said one or more inductor metal layers is positioned above said second metal layer.
3. The integrated circuit of claim 1 , wherein one of said one or more inductor metal layers is positioned below said second metal layer.
4. The integrated circuit of claim 1 , wherein a ratio defined by said third thickness and a minimum lateral dimension used in said one or more inductor metal layers is greater than a ratio defined by said second thickness and a minimum lateral dimension used in said second metal layer.
5. The integrated circuit of claim 1 , wherein two or more inductor metal layers are provided.
6. The integrated circuit of claim 5 , wherein at least two of said two or more inductor metal layers have metal lines with a different thickness.
7. The integrated circuit of claim 1 , wherein said third thickness is 3 μm or more.
8. The integrated circuit of claim 7 , wherein said third thickness is 4 μm or more.
9. The integrated circuit of claim 1 , wherein said plurality of semiconductor circuit elements are part of a circuitry that comprises an analog circuit portion and a digital circuit portion.
10. The integrated circuit of claim 1 , wherein a lateral dimension of said integrated circuit is defined by said plurality of semiconductor circuit elements formed in and above said semiconductor layer and by said first and second metal layers.
11. The integrated circuit of claim 1 , wherein the second metal layer does not include an inductor element.
12. The integrated circuit of claim 1 , wherein the semiconductor circuit elements form a part of a circuitry that comprises at least a first circuit portion and a second circuit portion, the integrated circuit further comprising:
a first interconnect and a second interconnect, the first interconnect forming at least part of an electrical connection between the first inductor and the first circuit portion and the second interconnect forming at least part of an electrical connection between the second inductor and the second circuit portion.
13. The integrated circuit of claim 12 , wherein:
the power and signal routing lines comprise a first routing line and a second routing line;
the first interconnect connects the first routing line with the first inductor; and
the second interconnect connects the second routing line with the second inductor.
14. The integrated circuit of claim 12 , wherein the first circuit portion comprises an analog circuit portion and the second circuit portion comprises a digital circuit portion.
15. The integrated circuit of claim 13 , wherein the first circuit portion comprises an analog circuit portion and the second circuit portion comprises a digital circuit portion.