Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information

1. A system comprising:

a memory subsystem having at least one memory device; and

a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem, and wherein the memory controller is configured to further:

receive a request to access the memory subsystem from a requestor;

convert the request into at least one memory command that is sent to the memory subsystem; and

translate an address of the request into an address of the memory subsystem to include in the at least one memory command, wherein translation of the address of the request into the address of the memory subsystem is based on mapping information that accounts for a reduction in available space for data in the memory subsystem due to storage of the ECC information in the first portion.

2. The system of claim 1 , wherein the memory subsystem includes a single memory device, wherein a first part of the memory device is to store data with ECC information, and a second part of the memory device is to store data without ECC information.

3. The system of claim 1 , wherein the memory controller is configured with configuration information to indicate that the first portion of the memory subsystem is to be protected by ECC information, and that the second portion of the memory subsystem is not to be protected by ECC information.

4. The system of claim 3 , wherein the memory controller includes at least one configuration register to store the configuration information.

5. The system of claim 1 , wherein the memory controller includes the mapping information that maps a first address space of the requestor to a second address space of the memory subsystem, and wherein the first address space is smaller than the second address space.

6. The system of claim 5 , wherein the translation of the address of the request into the address of the memory subsystem is based on the mapping information.

7. The system of claim 1 , wherein the memory controller is connected over a direct link to the memory subsystem.

8. A method comprising:

storing, by a memory controller, data with redundancy information in a first part of a memory device, and data without redundancy information in a second part of the memory device; and

storing mapping information in the memory controller, the mapping information mapping an address space of a requestor that uses the memory device to an address space of the memory device, wherein the address space of the requestor is smaller than the address space of the memory device.

9. The method of claim 8 , wherein storing data with the redundancy information comprises storing data with error correction code (ECC) information, and wherein storing data without redundancy information comprises storing data without ECC information.

10. The method of claim 8 , further comprising:

receiving, by the memory controller, a request from the requestor to access the memory device; and

translate an address of the request into an address in the address space of the memory device using the mapping information, wherein the address of the request is in the address space of the requestor.

11. The method of claim 10 , further comprising converting, by the memory controller, the request into one or more memory commands submitted to the memory device over a direct link between the memory controller and the memory device.

12. The method of claim 10 , wherein the translating of the address of the request into the address in the address space of the memory device accounts for a reduction in available space for data in the memory device due to storage of the redundancy information in the first part of the memory device.

13. A memory controller for use with a memory subsystem having at least one memory device, comprising:

a control circuit to send commands to the memory subsystem; and

a storage to store:

configuration information that indicates that a first portion of the memory subsystem is to store data with error correction code (ECC) information and a second portion of the memory subsystem is to store data without ECC information, and

mapping information that maps a first address space of a requestor that uses the memory subsystem to a second address space of the memory subsystem, wherein the first address space is smaller than the second address space.

14. The memory controller of claim 13 , wherein the control circuit is configured to further:

receive a request from the requestor to access the memory subsystem; and

translate, using the mapping information, an address of the request in the first address space into an address in the second address space.

15. The memory controller of claim 14 , wherein the control circuit is configured to further convert the request into one or more memory commands submitted to the memory subsystem over a direct link between the memory controller and the memory subsystem.

16. The memory controller of claim 13 , wherein the memory subsystem includes a single memory device.