Apparatus and methods to perform read-while write (RWW) operations
View Patent ↗Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
1. An apparatus comprising:
a plurality of block configurations of a memory array, some of said block configurations comprising an arrangement of similarly doped semiconductor switches, said block configurations to:
select a respective tile and,
for a particular memory cell of the respective tile, select a memory operation to be applied to the particular memory cell;
wherein immediately adjacent block configurations within a particular slice of the memory array are substantially mirrored, and wherein immediately adjacent block configurations in separate immediately adjacent slices of the memory array are substantially similar;
wherein similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations are arranged to electrically share a common potential signal value level; and
wherein each block configuration comprises a memory slice decoder and a memory operation decoder.
2. The apparatus of claim 1 , wherein the similarly doped semiconductor switches comprise field effect transistors (FETs).
3. The apparatus of claim 2 , wherein the similarly doped FETs comprise p-type FETs.
4. The apparatus of claim 2 , wherein drains of the similarly doped FETs within a block configuration are arranged to electrically share a common potential signal value level.
5. The apparatus of claim 2 , wherein said apparatus comprises at least one of the following: a memory device, cell phone, personal digital assistant, desktop computer, tablet computer, laptop computer or any combination thereof.
6. The apparatus of claim 1 , and further comprising: a decoder capable of providing signals to said block configurations for selection of a particular partition of the memory array.
7. The apparatus of claim 1 , wherein said block configurations in a particular slice of the memory array being capable of applying via a first electrical path a state read from a particular memory cell in the particular slice so that the state read becomes stored in sense circuitry.
8. The apparatus of claim 1 , wherein said block configurations in a particular slice of the memory array being capable of receiving via a second electrical path a state stored in sense circuitry, the state to be written to a particular memory cell in the particular slice.
9. The apparatus of claim 8 , wherein said block configurations in a particular slice of the memory array is capable of applying signals along the second electrical path to verify the state written to the particular memory cell in the particular slice.
10. The apparatus of claim 1 , wherein said block configurations are arranged to be capable of executing a read while write (RWW) operation.