IP Library Granted Patent US 8,867,818
Granted Patent B2
US 8,867,818 · App. 13/387,382 · Granted Oct 21, 2014

Method of creating template for matching, as well as device for creating template

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Quick Facts
Patent No.
US 8,867,818
App. No.
13/387,382
Granted
Oct 21, 2014
Kind
B2
Abstract

Disclosed is a method wherein a template for template matching is created with high accuracy and high efficiency. With respect to each individual pattern constituting a basic circuit, pattern information regarding a plurality of layers in a semiconductor device is stored in a library. On the basis of the designation of the position and the layer, pattern information regarding the designated position and layer is extracted from the pattern information stored in the library. A template is created on the basis of the extracted pattern information.

Claims (29)

1. A method of creating a template for performing template matching with a pattern on a semiconductor device, said method comprising the steps of:

specifying positional information and layer information about the semiconductor device;

extracting contour line data regarding the specified position and layer on the basis of the specified positional information and layer information from a library which stores contour line data, obtained in accordance with a scanning electron microscope image or simulation, of a plurality of layers for each one of a plurality of logic circuits present on the semiconductor device; and

registering the extracted contour line data of a part of one of the logic circuits as the template.

2. The method of creating a template of claim 1 ,

wherein data created on the basis of irradiation of the logic circuits with a charged particle beam, layout data about the logic circuits, mask data, or data created on the basis of irradiation of the mask formed based on the mask data with a charged particle beam are stored in said library.

3. The method of creating a template of claim 2 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam are contour line data obtained by extracting contour lines of images formed based on said irradiation by the charged particle beam.

4. The method of creating a template of claim 3 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam have been obtained by combining said contour line data so as to fully cover a region in which said logic circuits are formed.

5. A template creating device for creating a template for performing template matching with a pattern on a semiconductor device, said template creating device comprising:

a condition input portion for specifying positional information and layer information about the semiconductor device;

a storage medium storing a library in which contour line data, obtained in accordance with a scanning electron microscope image or simulation, of a plurality of layers for each one of a plurality of logic circuits present on the semiconductor device is stored; and

a processing portion for extracting contour line data of a part of one of the logic circuits from the library on the basis of the positional information and layer information entered from the condition input device and for creating the template on the basis of the extracted contour line data.

6. The template creating device of claim 5 ,

wherein data created on the basis of irradiation of the logic circuits with a charged particle beam, layout data about the logic circuits, mask data, or data created on the basis of irradiation of the mask formed based on the mask data with a charged particle beam are stored in said library.

7. The template creating device of claim 6 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam are contour line data obtained by extracting contour lines of images formed based on the irradiation by the charged particle beam.

8. The template creating device of claim 7 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam have been obtained by combining said contour line data so as to fully cover a region in which said logic circuits are formed.

9. A non-transitory computer readable medium storing a computer program executed by a computer connected with a charged particle beam instrument to create a template for performing template matching with a pattern formed on a sample, the charged particle beam instrument being operable to form an image by scanning a charged particle beam over the sample, said computer program performing the steps of steps of:

causing the computer to extract, on the basis of a designation of positional information and layer information about the sample, contour line data regarding the specified position and layer from a library storing contour line data, obtained in accordance with a scanning electron microscope image or simulation, of a plurality of layers for each one of a plurality of logic circuits present on the semiconductor device; and

registering the extracted contour line data of a part of one of the logic circuits regarding the specified position and layer as the template.

10. The non-transitory computer readable medium storing the computer program of claim 9 ,

wherein data created on the basis of irradiation of the logic circuits with the charged particle beam, layout data about the logic circuits, mask data, or data created on the basis of irradiation of the mask formed based on the mask data with the charged particle beam are stored in said library.

11. The non-transitory computer readable medium storing the computer program of claim 10 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam are contour line data obtained by extracting contour lines of images formed based on the irradiation by the charged particle beam.

12. The non-transitory computer readable medium storing the computer program of claim 11 ,

wherein the data created on the basis of irradiation of said logic circuits or said mask with the charged particle beam have been obtained by combining said contour line data so as to fully cover a region in which said logic circuits are formed.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Mar 30, 2020
From: HITACHI HIGH-TECHNOLOGIES CORPORATION
To: HITACHI HIGH-TECH CORPORATION
Reel/Frame 052259/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2012
From: MATSUOKA, RYOICHI; SUGIYAMA, AKIYUKI; TOYODA, YASUTAKA
To: HITACHI HIGH-TECHNOLOGIES CORPORATION
Reel/Frame 027604/0912 →