IP Library Granted Patent US 9,099,609
Granted Patent B2
US 9,099,609 · App. 13/392,410 · Granted Aug 4, 2015

Method of forming a non-polar/semi-polar semiconductor template layer on unevenly patterned substrate

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,099,609
App. No.
13/392,410
Granted
Aug 4, 2015
Kind
B2
Abstract

Provided are a high-quality non-polar/semi-polar semiconductor device with reduced defect density and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The manufacturing method is a method for manufacturing a semiconductor device, in which a template layer and a semiconductor device structure are formed on a sapphire substrate having a crystal plane for growing a non-polar or semi-polar nitride semiconductor layer. The sapphire substrate is etched to form uneven patterns, and the template layer including a nitride semiconductor layer and a GaN layer is formed on the sapphire substrate in which the uneven patterns are formed.

Claims (26)

1. A method for manufacturing a semiconductor device, the method comprising:

etching a sapphire substrate to form uneven patterns thereon, the sapphire substrate comprising an A-plane or M-plane crystal plane; and

forming a template layer on the etched sapphire substrate,

wherein forming the template layer comprises:

forming a low-temperature nitride semiconductor layer at a temperature in the range of 400 to 700° C.;

forming a high-temperature nitride semiconductor layer at a temperature in the range of 700 to 1100° C.; and

forming an undoped GaN layer at a temperature in the range of 800 to 1100° C., and

wherein the low-temperature nitride semiconductor layer of the template layer contacts the sapphire substrate.

2. The method of claim 1 , wherein the low-temperature nitride semiconductor layer and the high-temperature nitride semiconductor layer each comprise In x Al y Ga 1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1).

3. The method of claim 1 , wherein etching the sapphire substrate to form uneven patterns comprises:

forming photoresist patterns corresponding to the uneven patterns on the sapphire substrate; and

etching the photoresist patterns using an anisotropic etching process comprising inductively coupled plasma etching.

4. The method of claim 1 , wherein etching the sapphire substrate to form uneven patterns comprises:

forming photoresist patterns corresponding to the uneven patterns on the sapphire substrate; and

etching the photoresist patterns using an isotropic etching process using an acid solution or an alkali solution.

5. The method of claim 1 , wherein the uneven patterns comprise a polygonal shape, a circular shape, a semicircular shape, a triangular shape, or a rectangular shape.

6. The method of claim 1 , wherein an array of the uneven patterns is formed so that each uneven pattern comprises a width of 10 nanometers to 100 micrometers and a height of 10 nanometers to 100 micrometers, and an interval between each uneven pattern is 10 nanometers to 100 micrometers.

7. The method of claim 1 , further comprising:

forming a light-emitting diode (LED) layer on the template layer,

wherein forming the LED layer comprises growing an n-type nitride semiconductor layer on the template layer, growing at least one active layer on the n-type nitride semiconductor layer, and growing a p-type nitride semiconductor layer on the at least one active layer.

8. The method of claim 1 , further comprising:

coating a photoresist on the sapphire substrate before etching the sapphire substrate; and

exposing the photoresist using a photo mask comprising a pattern array,

wherein etching the sapphire substrate is performed using the exposed photoresist.

9. The method of claim 1 , wherein the template layer comprises a non-polar or semi-polar nitride semiconductor layer.

10. The method of claim 1 , wherein the thickness of each of the low-temperature nitride semiconductor layer, the high-temperature nitride semiconductor layer, and the undoped GaN layer is in the range of 10 to 20,000 Å.

Assignments (2)
CHANGE OF NAME Recorded Apr 21, 2014
From: SEOUL OPTO DEVICE CO., LTD
To: SEOUL VIOSYS CO., LTD
Reel/Frame 032723/0126 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2012
From: NAM, OK HYUN; YOO, GEUN HO
To: SEOUL OPTO DEVICE CO., LTD.; KOREA POLYTECHNIC UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
Reel/Frame 027766/0826 →