Granted Patent B2

US 8,924,795 · App. 13/393,589 · Granted Dec 30, 2014

Abstract

Claims (57)

1. A distributed debug system comprising:

a plurality of processing elements connected to sequentially perform a plurality of processing functions on a received data unit, wherein at least a first and a second of said processing elements comprise

a debug trap unit having

a first debug enable input,

a first debug enable output,

a first debug thread comprising at least a first debug trap circuit having a match signal output connected to said first debug enable output and configured to filter at least a part of said data unit, compare a filtering result with a configurable debug value and provide a match signal to said match signal output when a comparison result indicates a successful local match, and

a debug trace dump logic unit configured adapted to dump a configurable amount of debug trace data to a buffer associated with said data unit on reception of a match event; and

a debug initiator unit comprising

a debug initiator output connected to said first debug enable input of said debug trap unit of said first processing element, and

a debug initiator input connected to said first debug enable output of said debug trap unit of said second processing element.

2. The distributed debug system as claimed in claim 1 wherein said first debug enable output of the debug trap unit of said first processing element is connected to said first debug enable input of the debug trap unit of said second processing element.

3. The distributed debug system as claimed in claim 2 , wherein said first debug thread of at least one of said processing elements further comprises:

at least a second debug trap circuit, wherein

each of said first and second debug trap circuits comprises a match signal input, a match signal output, an AND/OR input and an AND/OR output, and

said inputs of said second debug trap circuit are connected to corresponding outputs of said first debug trap circuit.

4. The distributed debug system as claimed in claim 1 wherein said first debug thread of at least one of said processing elements further comprises:

at least a second debug trap circuit, wherein

each of said first and second debug trap circuits comprises a match signal input, a match signal output, an AND/OR input and an AND/OR output, and

said inputs of said second debug trap circuit are connected to corresponding outputs of said first debug trap circuit.

5. The distributed debug system as claimed in claim 1 wherein said debug trap unit further comprises:

at least a second debug thread;

a second debug enable input; and

a second debug enable output.

6. The distributed debug system as claimed in claim 5 wherein the debug trap unit further comprises:

a trap reassignment logic circuit configured to connect at least one debug trap circuit comprised in one of said debug threads to a debug trap circuit comprised in another of said debug threads when said one of said debug threads is in an always-match condition.

7. The distributed debug system as claimed in claim 1 further comprising a shared storage memory configured to store accumulated debug data.

8. The distributed debug system as claimed in claim 1 , wherein a trap selection logic is configured to control different data unit parts processed by different debug trap circuits that coherently relate to the same said data unit.

9. The distributed debug system as claimed in claim 1 , comprising a debug dump circuit configured to transfer accumulated debug trace data and said data unit associated with said debug trace data to an analyzer unit.

10. The distributed debug system as claimed in claim 9 , wherein said analyzer unit is located on the same semiconductor chip as the distributed debug system.

11. The distributed debug system as claimed in claim 9 , wherein said analyzer unit is located off a semiconductor chip comprising the distributed debug system.

12. The distributed debug system as claimed in claim 1 , wherein said debug trace dump logic unit is configured to set different levels of verbosity of said debug trace data.

13. The distributed debug system as claimed in claim 1 , wherein said system is an embedded system.

14. Anon-transitory computer readable storage medium, storing instructions executable by one or more of a plurality of processing elements connected to sequentially perform a plurality of processing functions on a received data unit, the instructions configured to perform steps comprising:

filtering at least a part of said received data unit;

comparing a result of said filtering with a configurable debug value;

providing a match signal to a match signal output when a comparison result indicates a successful local match, wherein

said match signal output is connected to a first debug enable output, and

said filtering, comparing, and providing executed by a first debug thread of a debug trap unit performed on at least a first and a second of said plurality of processing elements; and

dumping a configurable amount of debug trace data to a buffer associated with said received data unit, in response to said match signal, wherein said dumping is executed by a debug trace logic unit performed on at least the first and the second of said plurality of processing elements.

15. The non-transitory computer readable storage medium of claim 14 , storing further instructions, the further instructions configured to perform steps comprising:

transferring accumulated debug trace data and said data unit associated with said debug trace data to an analyzer unit, wherein said transferring instructions are executed by a debug dump circuit coupled to the one or more of the plurality of processing elements.

16. The non-transitory computer readable storage medium of claim 14 , storing further instructions, the further instructions configured to perform steps comprising:

connecting at least one debug trap circuit, comprised in the debug thread, to a debug trap circuit comprised in another debug thread when the debug thread is in an always-match condition.

17. A method comprising:

sequentially performing, at a plurality of processing elements, a plurality of processing functions on a received data unit;

filtering at least a part of said received data unit;

comparing a result of said filtering with a configurable debug value;

providing a match signal to a match signal output when a comparison result indicates a successful local match, wherein

said match signal output is connected to a first debug enable output, and

said filtering, comparing, and providing executed by a first debug thread of a debug trap unit performed on at least a first and a second of said plurality of processing elements; and

dumping a configurable amount of debug trace data to a buffer associated with said received data unit, in response to said match signal, wherein said dumping is executed by a debug trace logic unit performed on at least the first and the second of said plurality of processing elements.

18. The method of claim 17 , further comprising:

transferring accumulated debug trace data and said data unit associated with said debug trace data to an analyzer unit, wherein said transferring instructions are executed by a debug dump circuit coupled to the one or more of the plurality of processing elements.

19. The method of claim 17 , further comprising:

connecting at least one debug trap circuit, comprised in the debug thread, to a debug trap circuit comprised in another debug thread when the debug thread is in an always-match condition.

20. The method of claim 17 , further comprising:

controlling different data unit parts processed by different debug trap circuits that coherently relate to the same said data unit.

Assignments (31)