Method of manufacturing non-volatile memory devices

1. A method of manufacturing non-volatile memory devices, comprising:

forming a gate insulating layer and a first conductive layer over a semiconductor substrate;

etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate;

forming trenches at a target depth of the semiconductor substrate by repeatedly performing a dry etch process for etching the exposed semiconductor substrate and a cleaning process for removing residues generated in the dry etch process, wherein the cleaning process includes a wet cleaning process and a dry cleaning process;

forming isolation layers within the trenches;

forming a dielectric layer on a surface of an entire structure in which the isolation layers are formed; and

forming a second conductive layer on the dielectric layer.

2. The method of claim 1 , wherein the dry etch process is performed to etch the exposed semiconductor substrate deeper.

3. The method of claim 1 , wherein the cleaning process is performed to remove the residues while maintaining an etch depth of the semiconductor substrate.

4. The method of claim 1 , wherein the cleaning process includes a wet cleaning process while the semiconductor substrate is etched up to a set depth shallower than the target depth in the dry etch process.

5. The method of claim 1 , wherein the wet cleaning process is performed using an H 2 SO 4 solution.

6. The method of claim 1 , wherein the wet cleaning process is performed by loading the semiconductor substrate into single type equipment and supplying isoprophil alcohol (IPA) to the semiconductor substrate.

7. The method of claim 6 , wherein the IPA has a temperature of 50° C. to 80° C.

8. The method of claim 7 , wherein the temperature is reached by preheating a nozzle for spraying the IPA.

9. The method of claim 1 , wherein the dry cleaning process is performed using a mixed gas of nitrogen (N) and argon (Ar).

10. The method of claim 1 , wherein the first conductive layer is formed of a polysilicon layer of 500 Å to 1000 Å in thickness.

11. The method of claim 1 , wherein the second conductive layer is formed of a polysilicon layer.

12. A method of manufacturing non-volatile memory devices, comprising:

forming a gate insulating layer and a first conductive layer over a semiconductor substrate;

etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate;

forming trenches having a first depth shallower than a target depth by repeatedly performing a primary dry etch process for etching the exposed semiconductor substrate and a wet cleaning process for removing residues generated in the primary dry etch process;

performing a secondary dry etch process for the trenches to have the target depth;

performing a dry cleaning process for removing residues generated in the secondary dry etch process;

forming isolation layers within the trenches;

forming a dielectric layer on a surface of an entire structure in which the isolation layers are formed; and

forming a second conductive layer on the dielectric layer.

13. The method of claim 12 , wherein the wet cleaning process is performed using an H 2 SO 4 solution.

14. The method of claim 12 , wherein the wet cleaning process is performed by loading the semiconductor substrate into single type equipment and supplying isoprophil alcohol (IPA) to the semiconductor substrate.

15. The method of claim 12 , wherein the first depth is a depth such that patterns formed between the trenches by etching the exposed semiconductor substrate in the primary dry etch process are prevented from being inclined in the wet cleaning process.

16. A method of manufacturing non-volatile memory devices, comprising:

forming stack layers over a semiconductor substrate, wherein the stack layers comprise a gate insulating layer, a first conductive layer for floating gates, a dielectric layer, and a second conductive layer for control gates;

forming mask patterns on the stack layers;

repeating a dry etch process and a wet cleaning process to etch the stack layer exposed between the mask patterns up to a first depth; and

patterning the stack layers to be etched up to a target depth by performing a dry etch process when the stack layers are etched up to the first depth.

17. The method of claim 16 , wherein the wet cleaning process is performed using an H 2 SO 4 solution.

18. The method of claim 16 , wherein the wet cleaning process is performed by loading the semiconductor substrate into single type equipment and supplying isoprophil alcohol (IPA) to the semiconductor substrate.