Nonvolatile memory device and operating method thereof
A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
1. A nonvolatile memory device comprising:
a channel vertically extending from a substrate;
a plurality of memory cells stacked along the channel;
a source region connected to a first end portion of the channel; and
a bit line connected to a second end portion of the channel,
wherein the first end portion of the channel is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities and is only in contact with the source region over the source region or under the source region,
wherein the second end portion of the channel is formed of a semiconductor material of which a conductivity type is different from that of the first end portion, and
wherein an intermediate portion of the channel between the first end portion and the second end portion is formed of a semiconductor material of which a conductivity type is same as that of the first end portion.
2. The nonvolatile memory device of claim 1 , wherein the first end portion is formed of the undoped semiconductor layer,
wherein the second end portion is formed of a semiconductor material doped with P-type impurities or N-type impurities, and
wherein the intermediate portion is formed of an undoped semiconductor material.
3. The nonvolatile memory device of claim 1 , wherein the first end portion is formed of the semiconductor layer doped with P-type impurities,
wherein the second end portion is formed of an undoped semiconductor material or a semiconductor material doped with N-type impurities, and
wherein the intermediate portion is formed of a semiconductor material doped with P-type impurities.
4. The nonvolatile memory device of claim 1 ,
wherein the plurality of memory cells comprise a plurality of floating gate electrodes and a plurality of control gate electrodes that are alternately stacked along the channel,
wherein each memory cell comprises one floating gate electrode and two control gate electrodes that are disposed over and under the floating gate electrode,
wherein two adjacent memory cells share one control gate electrode, and
wherein a tunnel dielectric layer is interposed between the channel and the memory cells.
5. The nonvolatile memory device of claim 1 ,
wherein the channel comprises:
a pair of pillar portions vertically extending from the substrate; and
a connection portion connecting lower ends of the pair of pillar portions,
wherein the plurality of memory cells comprise a plurality of floating gate electrodes and a plurality of control gate electrodes that are alternately stacked along the respective pillar portions of the channel,
wherein each memory cell comprises one floating gate electrode and two control gate electrodes that are disposed over and under the floating gate electrode,
wherein two adjacent memory cells share one control gate electrode, and
wherein a tunnel dielectric layer is interposed between the channel and the memory cells.
6. The nonvolatile memory device of claim 4 , further comprising:
a charge blocking layer covering all surfaces of the floating gate electrodes except a surface of the floating gate electrodes that faces the tunnel dielectric layer.
7. The nonvolatile memory device of claim 1 ,
wherein the plurality of memory cells comprise a plurality of interlayer dielectric layers and a plurality of control gate electrodes that are alternately stacked along the channel and a memory layer that is interposed between the control gate electrodes and the channel, and
wherein the memory layer comprises a tunnel dielectric layer, a charge storage layer, and a charge blocking layer.
8. The nonvolatile memory device of claim 1 ,
wherein the channel comprises:
a pair of pillar portions vertically extending from the substrate; and
a connection portion connecting lower ends of the pair of pillar portions,
wherein the plurality of memory cells comprise a plurality of interlayer dielectric layers and a plurality of control gate electrodes that are alternately stacked along the respective pillar parts of the channel and a memory layer that is interposed between the control gate electrodes and the channel, and
wherein the memory layer comprises a tunnel dielectric layer, a charge storage layer, and a charge blocking layer.
9. The nonvolatile memory device of claim 1 , further comprising:
a first selection transistor formed between the plurality of memory cells and the source region; and
a second selection transistor formed between the plurality of memory cells and the bit line,
wherein the first end portion corresponds to a portion of the channel between the source region and a gate electrode of the first selection transistor.
10. The nonvolatile memory device of claim 2 , further comprising:
a first selection transistor formed between the plurality of memory cells and the source region; and
a second selection transistor formed between the plurality of memory cells and the bit line,
wherein the first end portion corresponds to a portion of the channel between the source region and a gate electrode of the first selection transistor, and
wherein the second end portion corresponds to a portion of the channel between the bit line and a gate electrode of the second selection transistor.