Clock recovery system
View Patent ↗In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator.
1. A low-power clock recovery system comprising:
plural clock recovery circuits that are for coupling to plural wired data lanes, the plural wired data lanes to provide plural data streams, the plural clock recovery circuits to recover a clock from each of the data streams, each clock recovery circuit including
a phase comparator receiving an incoming signal from one of the plural data streams from which a clock signal is to be derived, the incoming signal to be compared to a mixed clock signal;
a filter coupled to an output of the phase comparator;
a frequency synthesizer coupled to an output of the filter, wherein the frequency synthesizer comprises a numerically controlled oscillator to generate respective in-phase and quadrature-phase digital clock signatures;
a digital-to-analog converter (DAC) to receive the in-phase and quadrature-phase clock signatures, and to generate respective analog in-phase and quadrature-phase clock signals; and
an image rejecting mixer to mix the analog in-phase and quadrature-phase clock signals with respective in-phase and quadrature-phase master clock signals to generate the mixed clock signal, the mixed clock signal fed back as a single-tone input signal to the phase comparator.
2. The clock recovery system of claim 1 , wherein the frequency synthesizer is designed to receive a control signal generated by a bang-bang phase detection scheme.
3. The clock recovery system of claim 1 , wherein the frequency synthesizer is designed to receive a control signal generated by a Mueller-Muller phase-detection scheme.
4. The clock recovery system of claim 1 , wherein the frequency synthesizer is designed to receive a control signal generated by a linear phase-frequency detection scheme.
5. The clock recovery system of claim 1 , wherein a dithering signal generator is coupled between an integrator and the frequency synthesizer.
6. The clock recovery system of claim 1 , wherein the filter can be of any order.
7. A low-power clock recovery system comprising:
plural clock recovery circuits that are for coupling to plural wired data lanes, the plural wired data lanes to provide plural data streams, the plural clock recovery circuits to recover a clock from each of the data streams, each clock recovery circuit including
a phase comparator receiving an incoming signal from one of the plural data streams containing clock information, the incoming signal to be compared to a mixed clock signal;
a filter coupled to an output of the phase comparator;
a frequency synthesizer coupled to an output of the filter to generate in-phase clock and quadrature clock signatures;
a digital-to-analog converter (DAC) to receive the in-phase and quadrature-phase clock signatures, and to generate respective analog in-phase and quadrature-phase clock signals;
a mixer to mix the analog in-phase clock output and the analog quadrature clock output of the frequency synthesizer with an in-phase master clock signal and a quadrature master clock signal to generate the mixed clock signal, the mixed clock signal fed back as a single-tone input to the phase comparator; and
wherein the frequency synthesizer is a numerically controlled oscillator (NCO).
8. The clock recovery system of claim 7 , wherein the mixer is an image rejecting mixer mixing the in-phase clock and the quadrature clock with an in-phase master clock and a quadrature master clock.
9. The clock recovery system of claim 7 , wherein the clock recovery system further includes an image rejecting filter coupled to the output of the filter.
10. The clock recovery system of claim 7 , wherein a dithering signal generator is coupled between the filter and the frequency synthesizer.