Programmable cryptographic integrated circuit

1. A cryptographic integrated circuit comprising:

a programmable main processor configured to execute cryptographic functions;

an internal memory;

a data transmission bus to which the main processor and the internal memory are electrically connected; and

a programmable arithmetic coprocessor also electrically connected to the data transmission bus and being separate from the main processor, and comprising

a plurality of specific hardware arithmetic units each configured to perform a predetermined arithmetical operation;

a programmable sequencer that is electrically connected to each of the specific hardware arithmetic units and that includes additional arithmetic units;

an input/output interface that can be connected to the data transmission bus;

a command scheduler that interfaces between the input/output interface and the programmable sequencer; and

a local memory that is electrically connected to the programmable sequencer and to each of the specific hardware arithmetic units,

wherein the hardware architecture of at least one of the plurality of specific hardware arithmetic units is configured to perform modular arithmetical operations in a pipeline mode and to return several possible values from a requested single arithmetical operation, and also a parameter for selecting a single value from among said several possible values.

2. The cryptographic integrated circuit according to claim 1 , in which a hardware architecture of each specific hardware arithmetic unit in the arithmetic coprocessor is configured to perform operations on numbers that are binary-coded in words of at least 128 bits, designated as “large numbers”.

3. The cryptographic integrated circuit according to claim 1 , in which the programmable arithmetic coprocessor comprises at least one hardware arithmetic unit configured to perform modular addition, one hardware arithmetic unit configured to perform modular multiplication using Montgomery reduction, and one hardware arithmetic unit configured to perform a modular logic operation.

4. The cryptographic integrated circuit according to claim 1 , in which the programmable arithmetic coprocessor comprises an output status register comprising a storage space of said selection parameter.

5. The cryptographic integrated circuit according to claim 1 , in which the hardware architecture of each additional arithmetic unit of the programmable sequencer is configured to perform operations on numbers that are binary-coded in words of at most 64 bits.

6. The cryptographic integrated circuit according to claim 1 , in which the programmable sequencer further comprises:

a controller for executing microprograms;

a microcode memory; and

multiple registers including an input command register that is writable by the command scheduler and an output status register that is readable by the command scheduler.

7. The cryptographic integrated circuit according to claim 6 , in which the microcode memory comprises program instructions for carrying out at least one of the operations from the set consisting of a modular multiplication, a modular exponentiation, a modular inverse calculation, a modular division, and an elliptic curve scalar multiplication, using the specific hardware arithmetic units and the additional arithmetic units.

8. The cryptographic integrated circuit according to claim 7 , in which the programmable main processor and the programmable arithmetic coprocessor communicate according to a programming interface providing at least a portion of a set of arithmetic calculation commands sent to the programmable arithmetic coprocessor by the main processor containing a field to indicate whether the modularity parameter for a modular arithmetical calculation is maintained from a previous calculation.