Non-volatile memory cell and logic transistor integration
View Patent ↗A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.
1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a charge storage layer over the substrate in the NVM region and the logic region;
forming a first conductive layer over the charge storage layer in the NVM region and the logic region;
patterning the first conductive layer and the charge storage layer to form a control gate in the NVM region and to remove the first conductive layer and the charge storage layer from the logic region;
forming a first dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
forming a sacrificial layer over the first dielectric layer in the NVM region and the logic region;
planarizing the sacrificial layer, wherein the first dielectric layer comprises a sidewall portion located along a sidewall of the control gate, between the control gate and the sacrificial layer;
forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the first sacrificial layer and the control gate in the NVM region and a second masking portion over the first sacrificial layer in the logic region, wherein:
the first masking portion defines a select gate location laterally adjacent the control gate in the NVM region; and
the second masking portion defines a logic gate location in the logic region;
using the patterned masking layer to remove exposed portions of the sacrificial layer, wherein a first portion of the sacrificial layer remains at the select gate location and a second portion of the sacrificial layer remains at the logic gate location;
forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location;
forming a gate dielectric layer over the second dielectric layer and within the first and second openings; and
forming a select gate within the first opening and a logic gate within the second opening.
2. The method of claim 1 , wherein the step of planarizing the sacrificial layer exposes the first dielectric layer located on the control gate, and wherein the step of forming the patterned masking layer is performed such that:
the first masking portion is directly over the control gate, and
a first edge of the first masking portion extends laterally from the control gate onto the first sacrificial layer to define the select gate location laterally adjacent the control gate in the NVM region.
3. The method of claim 2 , wherein the step of forming the patterned masking layer is performed such that a second edge of the first masking portion, opposite the first edge of the first masking portion, is formed directly on the sidewall portion of the first dielectric layer.
4. The method of claim 2 , wherein the step of forming the patterned masking layer is performed such that a second edge of the first masking portion, opposite the first edge of the first masking portion, is aligned to a center of the sidewall portion of the first dielectric layer, wherein the center corresponds to a center point of a line which extends between the control gate and the sacrificial layer and is substantially perpendicular to sidewalls of the control gate and sacrificial layer.
5. The method of claim 1 , wherein the step of forming the first dielectric layer is performed such that a thickness of the sidewall portion of the first dielectric layer is in a range of 60 to 150 Angstroms.
6. The method of claim 1 , wherein the step of removing the first portion and the second portion of the sacrificial layer is performed such that at least a portion of the sidewall portion of the first dielectric layer remains.
7. The method of claim 6 , further comprising:
after the step of removing the first portion and the second portion of the sacrificial layer, performing an isotropic etch of the first dielectric layer to thin the at least a portion of the sidewall portion.
8. The method of claim 1 , wherein the step of forming the select gate is characterized in that, after the select gate is formed, a portion of the gate dielectric layer and a portion of the first dielectric layer are located between the select gate and the control gate.
9. The method of claim 1 , wherein after the step of using the patterned masking layer to remove exposed portions of the sacrificial layer and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the first portion of the sacrificial layer, a second source/drain region in the substrate laterally adjacent the control gate such that the first portion of the sacrificial layer and the control gate are located between the first and second source/drain regions; and
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the sacrificial layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the sacrificial layer.
10. The method of claim 9 , wherein after the step of using the patterned masking layer to remove exposed portions of the sacrificial layer and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first sidewall spacer surrounding outer sidewalls of the first portion of the sacrificial layer and the control gate and a second sidewall spacer surrounding the second portion of the sacrificial layer.
11. The method of claim 1 , further comprising:
prior to the step of forming the charge storage layer, forming a masking layer over the substrate in the logic region, wherein the charge storage layer is formed on the substrate in the NVM region and on the masking layer in the logic region; and
prior to the step of forming the first dielectric layer, removing the masking layer.
12. The method of claim 1 , wherein the step of forming the charge storage layer comprises:
forming a bottom dielectric layer;
forming nanocrystals over the bottom dielectric layer; and
forming a top dielectric layer over the bottom dielectric layer and over and around the nanocrystals.
13. The method of claim 12 , wherein forming the bottom dielectric layer is characterized in that the bottom dielectric layer comprises a dielectric material having a high dielectric constant and forming the nanocrystals is characterized in that the nanocrystals comprise a metal.
14. The method of claim 1 , wherein the step of forming the select gate and the logic gate is characterized in that the select gate and logic gate are formed from a same metal layer.
15. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a nanocrystal stack layer over the substrate in the NVM region and the logic region;
forming a first conductive layer over the nanocrystal stack layer in the NVM region and the logic region;
patterning the first conductive layer and the nanocrystal stack layer to form a control gate in the NVM region and to remove the first conductive layer and the nanocrystal stack layer from the logic region;
forming a first dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
forming a sacrificial layer over the first dielectric layer in the NVM region and the logic region;
planarizing the sacrificial layer to expose the first dielectric layer located on the control gate, wherein the first dielectric layer comprises a sidewall portion located between the control gate and the sacrificial layer;
forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the sacrificial layer and the control gate in the NVM region and a second masking portion over the sacrificial layer in the logic region, wherein:
the first masking portion is directly over the control gate, a first edge of the first masking portion extends laterally from the control gate onto the sacrificial layer to define a select gate location laterally adjacent the control gate in the NVM region, and a second edge of the first masking portion, opposite the first edge of the first masking portion, is directly on the sidewall portion; and
the second masking portion defines a logic gate location in the logic region;
using the patterned masking layer to remove exposed portions of the sacrificial layer, wherein a first portion of the sacrificial layer remains at the select gate location and a second portion of the sacrificial layer remains at the logic gate location;
forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location;
forming a gate dielectric layer over the second dielectric layer and within the first and second openings; and
forming a select gate within the first opening and a logic gate within the second opening, wherein, after the select gate is formed, a portion of the gate dielectric layer and a portion of the first dielectric layer remains between the select gate and the control gate.
16. The method of claim 15 , wherein the step of forming the first dielectric layer is performed such that a thickness of the sidewall portion of the first dielectric layer is in a range of 60 to 150 Angstroms.
17. The method of claim 15 , further comprising:
after the step of removing the first portion and the second portion of the sacrificial layer, performing an isotropic etch of the first dielectric layer to thin the sidewall portion.
18. The method of claim 15 , wherein after the step of using the patterned masking layer to remove exposed portions of the sacrificial layer and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the first portion of the sacrificial layer, a second source/drain region in the substrate laterally adjacent the control gate such that the first portion of the sacrificial layer and the control gate are located between the first and second source/drain regions;
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the sacrificial layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the sacrificial layer; and
forming a first sidewall spacer surrounding outer sidewalls of the first portion of the sacrificial layer and the control gate and a second sidewall spacer surrounding the second portion of the sacrificial layer.