Methods of forming memory structures and methods of forming memory arrays

1. A method of forming a plurality of memory structures, comprising:

forming a line of electrically insulative material over a base; the line having a first sidewall in opposing relation to a second sidewall; the base having a plurality of spaced-apart electrical contact regions along an upper surface; the first sidewall being directly over an upper surface of a first electrical contact region and the second sidewall being directly over a second electrical contact region;

depositing electrode material over the line and along the sidewalls;

patterning the electrode material to form a first electrode along the first sidewall and to form a second electrode along the second sidewall; the first and second electrodes being electrically coupled with the first and second electrical contact regions, respectively;

forming programmable material over the first and second electrodes; and

forming a top electrode over the programmable material; a first memory cell comprising the first electrode together with the programmable material and the top electrode, and a second memory cell comprising the second electrode together with the programmable material and the top electrode; the programmable material within the first and second memory cells being a continuous strap across the first and second electrodes.

2. The method of claim 1 wherein:

the base comprises buried wordlines;

the electrical contact regions are source/drain regions paired with individual buried wordlines to form transistors; and

the first electrical contact region is comprised by a first transistor, and the second electrical contact region is comprised by a second transistor adjacent the first transistor.

3. The method of claim 1 wherein the sidewalls are substantially orthogonal relative to a planar topography of the base.

4. The method of claim 1 wherein the sidewalls are at an angle of from greater than 30° to less than or equal to about 85° relative to a planar topography of the base.

5. The method of claim 1 wherein each of the first and second sidewalls comprises at least two angled segments between a planar topography of the base and a top surface of the line.

6. The method of claim 1 wherein the electrode material comprises titanium nitride.

7. The method of claim 1 wherein the first and second electrodes have thicknesses of less than or equal to about 10 nanometers.

8. The method of claim 1 wherein the memory cells are RRAM cells.

9. A method of forming a memory array, comprising:

forming spaced-apart lines of electrically insulative material over a base; each line having a pair of opposing sidewalls; the base having a plurality of spaced-apart electrical contact strips along an upper surface; the sidewalls of the lines being directly over upper surfaces of the electrical contact strips;

depositing electrode material across the lines and across spaces between the lines;

patterning the lines and strips into spaced-apart slices; the patterning dividing the electrical contact strips into a plurality of contact regions, and dividing the lines into electrically insulative projections;

patterning the electrode material into a plurality of bottom electrodes, with each bottom electrode being electrically coupled to a contact region; the bottom electrodes and electrically insulative projections being together comprised by paired-bottom-electrode structures having a single electrically insulative projection between a pair of bottom electrodes;

forming programmable material over the paired-bottom-electrode structures; and

forming top electrodes over the programmable material; the top electrodes being in one-to-one correspondence with the paired-bottom-electrode structures; individual memory cells of the memory array comprising a bottom electrode together with the programmable material and a top electrode.

10. The method of claim 9 further comprising:

forming electrically insulative material over and between the spaced-apart slices;

forming a planarized surface extending across the paired-cell structures and the electrically insulative material; and

forming the programmable material over the planarized surface.

11. The method of claim 9 wherein the programmable material is formed as a plurality of separate programmable material straps, and wherein each strap is across only a single paired-bottom-electrode structure.

12. The method of claim 9 wherein the programmable material is formed as a continuous expanse extending across multiple paired-bottom-electrode structures.

13. The method of claim 9 wherein:

the base comprises buried wordlines;

the electrical contact regions are source/drain regions paired with individual buried wordlines to form transistors; and

individual paired-bottom electrode structures have a first bottom electrode and a second bottom electrode, with the first bottom electrode being connected to a source/drain region of a different transistor than the second bottom electrode.

14. The method of claim 9 wherein the sidewalls of the lines are substantially orthogonal relative to a planar topography of the base.

15. The method of claim 9 wherein the sidewalls of the lines are at an angle of from greater than or equal to about 45° to less than or equal to about 60° relative to a planar topography of the base.

16. The method of claim 9 wherein each of the sidewalls of the lines comprises at least two segments having different angles than one another relative to a planar topography of the base.

17. The method of claim 9 wherein the memory cells are RRAM cells.