Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.
1. A nonvolatile memory device comprising:
a substrate having active regions that are defined by an isolation layer and that have first sidewalls and second sidewalls which are opposite to the first sidewalls, wherein portions of the first sidewalls of the active regions towers above the isolation layer;
floating gates having first portions facing the portions of the first sidewalls of the active regions and second portions towering above the active regions, wherein the floating gates do not face the second sidewalls of the active regions;
a tunnel dielectric layer interposed between the active regions and the floating gates;
an intergate dielectric layer disposed over the floating gates; and
a control gate disposed over the intergate dielectric layer.
2. The nonvolatile memory device of claim 1 , wherein the control gate faces first sidewalls of the second portions of the floating gates, and the control gate does not face second sidewalls of the second portions of the floating gates.
3. The nonvolatile memory device of claim 2 ,
wherein first and second spaces are alternately and repeatedly defined between the second portions of the floating gates, the first spaces being narrower than the second spaces, and
wherein the first sidewalls of the floating gates face the second spaces.
4. The nonvolatile memory device of claim 3 ,
wherein the second sidewalls of the floating gates face the first spaces, and
wherein the first spaces are filled with the intergate dielectric layer.
5. The nonvolatile memory device of claim 3 ,
wherein the second sidewalls of the floating gates face the first spaces,
wherein the first spaces are filled with a dielectric layer, and
wherein the intergate dielectric layer is disposed over the dielectric layer.
6. The nonvolatile memory device of claim 1 , wherein the floating gates have bent portions so that the second portions of the floating gates face upper surfaces of the active regions.
7. The nonvolatile memory device of claim 1 , wherein the floating gates have a rectangular shape so that the second portions of the floating gates do not face upper surfaces of the active regions.
8. The nonvolatile memory device of claim 1 ,
wherein first isolation regions and second isolation regions are alternately and repeatedly defined between the active regions, the first isolation regions being narrower than the second isolation regions, and
wherein the first sidewalls of the active regions face the second isolation regions.
9. The nonvolatile memory device of claim 1 , wherein the control gate faces first sidewalls and second sidewalls of the second portions of the floating gates.
10. The nonvolatile memory device of claim 1 ,
wherein isolation regions of the same width are defined between the active regions, and
wherein the first sidewalls of the active regions face the same direction.