Three dimensional pipe gate nonvolatile memory device
A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.
1. A nonvolatile memory device comprising:
a pipe gate having a pipe channel hole;
a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate;
a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole;
a first blocking layer and a charge trapping and charge storage layer and formed on sidewalls of the columnar cell channels;
a second blocking layer formed between the first blocking layer and the plurality of gate electrodes: and
a third blocking layer formed between the plurality of gate electrode and the plurality of interlayer insulation layers.
2. The nonvolatile memory device of claim 1 , further comprises a tunnel insulation layer formed between the columnar cell channels and the charge trapping and charge storage layer.
3. The nonvolatile memory device of claim 1 , wherein each of the second blocking layer and the third blocking layer includes a silicon oxide layer, a High-k layer including an aluminum oxide layer, or a combination thereof.
4. The nonvolatile memory device of claim 1 , wherein the pipe gate surrounds sidewalls of the pipe channel hole.
5. The nonvolatile memory device of claim 4 , further comprises:
a capping layer formed between the pipe gate and a lowermost interlayer insulation layer.
6. The nonvolatile memory device of claim 5 , wherein the capping layer includes a doped polysilicon layer.
7. The nonvolatile memory device of claim 1 , wherein the pipe gate surrounds sidewalls and a bottom of the pipe channel hole.
8. The nonvolatile memory device of claim 7 , further comprises:
a capping layer formed between the pipe gate and a lowermost interlayer insulation layer.
9. The nonvolatile memory device of claim 8 , wherein the capping layer includes a doped polysilicon layer.
10. The nonvolatile memory device of claim 1 , further comprises:
an etch stop layer formed between the pipe gate and a lowermost interlayer insulation layer.
11. The nonvolatile memory device of claim 10 , wherein the etch stop layer includes a material having etch selectivity with respect to the gate electrode and the interlayer insulation layer.
12. The nonvolatile memory device of claim 11 , wherein the etch stop layer includes an undoped polysilicon layer.