Granted Patent B2

US 9,142,607 · App. 13/403,743 · Granted Sep 22, 2015

Abstract

Claims (30)

1. An integrated MIM capacitor structure suitable for inclusion in a semiconductor device, the capacitor structure comprising:

a first metallization level overlying a substrate, the first metallization level including a first metallization plate overlying a capacitor region of the substrate;

a MIM capacitor, comprising:

the first metallization plate;

a MIM capacitor dielectric overlying the first metallization plate; and

an electrically conductive MIM capacitor plate overlying the MIM capacitor dielectric; and

a parasitic capacitor, comprising:

a second metallization plate comprising a portion of a second metallization level overlying the capacitor region;

a parasitic capacitor dielectric including an interlevel dielectric underlying the second metallization plate; and

a parasitic capacitor plate underlying the interlevel dielectric;

wherein a structure of the first metallization plate is selected from a fingered structure and a convex plate structure, a structure of the second metallization plate is selected from a fingered structure and a convex plate structure, and wherein the fingered structured includes a plurality of conductive fingers extending from a common connector;

wherein the fingered structure includes a plurality of rectangular fingers, each having a finger depth and a finger length, each adjacent pair of fingers separated by a finger spacing; and

wherein a ratio of a finger width to the finger spacing is approximately equal to 4.

2. The capacitor structure of claim 1 , wherein the parasitic capacitor plate comprises the MIM capacitor plate.

3. The capacitor structure of claim 2 , further comprising:

an electrically conductive via connecting the second metallization plate to the first metallization plate; and

a routing element comprising a portion of the second metallization level, wherein the routing element is connected to the MIM capacitor plate.

4. The capacitive structure of claim 1 , wherein a metallization density of the fingered structure is approximately equal to 80%.

5. A semiconductor fabrication process, comprising:

forming a first metallization level overlying a substrate including a capacitor region and a field region, the first metallization level including a first metallization plate overlying the capacitor region;

forming a capacitor dielectric overlying the first metallization plate;

forming a capacitor plate overlying the capacitor dielectric;

forming an interlevel dielectric layer overlying the capacitor plate; and

forming a second metallization level overlying the interlevel dielectric layer, the second metallization level including a second metallization plate overlying the capacitor region;

wherein forming at least one of the first metallization level and the second metallization level includes a patterning of a metallization level to define a fingered structure, the fingered structure including a plurality of electrically coupled finger elements, wherein adjacent finger elements are separated by a minimum spacing;

wherein the finger elements have a finger width; and

wherein a spacing-to-period ratio of the fingered structure is approximately equal to 20%.

6. The semiconductor fabrication process of claim 5 , further comprising:

prior to forming the interlevel dielectric layer, forming a second capacitor dielectric overlying the first capacitor plate;

forming a second capacitor plate overlying the second capacitor dielectric.

Assignments (31)