Stage circuit and bidirectional emission control driver using the same
A stage circuit includes an output unit for outputting the voltage of a first or second power source to a first output terminal, corresponding to a voltage at a first or second node; a bidirectional driver for receiving sampling signals of previous and next stages; a first driver coupled to the bidirectional driver to control the voltages at the first and second nodes, corresponding to first and second clock signals; and a second driver coupled to the bidirectional driver to output a sampling signal corresponding to the first and second clock signals. The first driver includes a first transistor coupled between the first power source and the second node; a second transistor coupled between the second node and the second power source; a third transistor coupled between the bidirectional driver and the first node; and a first capacitor coupled between the second node and a second input terminal.
1. A stage circuit for a current stage, comprising:
an output unit comprising fourth and fifth transistors for outputting voltages of first and second power sources, respectively, to a first output terminal according to voltages at first and second nodes, respectively, the first and second node voltages being voltages of gate electrodes of the fourth and fifth transistors, respectively;
a bidirectional driver for receiving sampling signals of previous and next stages;
a first driver coupled to the bidirectional driver and configured to control the voltages at the first and second nodes, corresponding to first and second clock signals; and
a second driver coupled to the bidirectional driver and configured to output a sampling signal of the current stage corresponding to the first and second clock signals,
wherein the first driver comprises:
a first transistor coupled between the first power source and the second node, and comprising a gate electrode coupled to the first node;
a second transistor coupled between the second node and the second power source, and comprising a gate electrode coupled to a first input terminal;
a third transistor coupled between the bidirectional driver and the first node, and comprising a gate electrode coupled to the first input terminal; and
a first capacitor coupled between the second node and a second input terminal.
2. The stage circuit according to claim 1 , wherein the first driver further comprises a second capacitor coupled between the first node and the first power source.
3. The stage circuit according to claim 1 , wherein the first input terminal is configured to receive the first clock signal and the second input terminal is configured to receive the second clock signal.
4. The stage circuit according to claim 1 , wherein the first and second clock signals are configured to be supplied during different horizontal periods from each other.
5. The stage circuit according to claim 1 , wherein the first power source is set to have a higher voltage than the second power source.
6. The stage circuit according to claim 1 , wherein
the fourth transistor is coupled between the first power source and the first output terminal, the gate electrode of the fourth transistor being coupled to the first node,
the fifth transistor is coupled between the first output terminal and the second power source, the gate electrode of the fifth transistor being coupled to the second node, and
the output unit further comprises a third capacitor coupled between the first power source and the first output terminal.
7. The stage circuit according to claim 1 , wherein the second driver comprises:
a sixth transistor coupled between the first power source and a second output terminal, and comprising a gate electrode coupled to the first output terminal;
a seventh transistor coupled between the second output terminal and the second input terminal, and comprising a gate electrode coupled to a third node;
an eighth transistor coupled between the third node and the bidirectional driver, and comprising a gate electrode coupled to the first input terminal; and
a fourth capacitor coupled between the third node and the second output terminal.
8. The stage circuit according to claim 1 , wherein the bidirectional driver comprises:
a ninth transistor coupled between the previous stage and a fourth node that is a common terminal of the first and second drivers, and comprising a gate electrode configured to receive a first control signal; and
a tenth transistor coupled between the next stage and the fourth node, and comprising a gate electrode configured to receive a second control signal.
9. The stage circuit according to claim 8 , wherein the first and second control signals are configured to be supplied without overlapping each other.
10. The stage circuit according to claim 1 , further comprising an eleventh transistor coupled between the first node and the second power source, and comprising a gate electrode configured to receive a reset signal.
11. The stage circuit according to claim 10 , wherein the reset signal is configured to be supplied at least once when power is turned on or off.
12. The stage circuit according to claim 1 , further comprising a twelfth transistor coupled between the first capacitor and the second input terminal, and comprising a gate electrode coupled to the second node.
13. An emission driver for supplying an emission control signal to emission control lines to control emission of pixels, the emission driver comprising the stage circuit according to claim 1 , coupled to one of the emission control lines.
14. A stage circuit for a current stage, comprising:
an output unit for outputting a voltage of a first or second power source to a first output terminal, corresponding to a voltage at a first or second node;
a bidirectional driver for receiving sampling signals of previous and next stages;
a first driver coupled to the bidirectional driver and configured to control the voltages at the first and second nodes, corresponding to first and second clock signals; and
a second driver coupled to the bidirectional driver and configured to output a sampling signal of the current stage corresponding to the first and second clock signals,
wherein the first driver comprises:
a first transistor coupled between the first power source and the second node, and comprising a gate electrode coupled to the first node;
a second transistor coupled between the second node and the second power source, and comprising a gate electrode coupled to a first input terminal;
a third transistor coupled between the bidirectional driver and the first node, and comprising a gate electrode coupled to the first input terminal; and
a first capacitor coupled between the second node and a second input terminal, and
wherein the first transistor has a lower resistance than the second transistor.
15. An emission driver for supplying an emission control signal to emission control lines via corresponding stages to control emission of pixels, the emission driver comprising a stage circuit for each of the stages and coupled to a respective one of the emission control lines, wherein the stage circuit for a current one of the stages comprises:
an output unit comprising fourth and fifth transistors for outputting voltages of first and second power sources, respectively, to a first output terminal coupled to the respective one of the emission control lines according to voltages at first and second nodes, respectively, the first and second node voltages being voltages of gate electrodes of the fourth and fifth transistors, respectively;
a bidirectional driver for receiving sampling signals of previous and next ones of the stages;
a first driver coupled to the bidirectional driver and configured to control the voltages at the first and second nodes, corresponding to first and second clock signals; and
a second driver coupled to the bidirectional driver and configured to output a sampling signal of the current one of the stages corresponding to the first and second clock signals,
wherein the first driver comprises:
a first transistor coupled between the first power source and the second node, and comprising a gate electrode coupled to the first node;
a second transistor coupled between the second node and the second power source, and comprising a gate electrode coupled to a first input terminal;
a third transistor coupled between the bidirectional driver and the first node, and comprising a gate electrode coupled to the first input terminal; and
a first capacitor coupled between the second node and a second input terminal.
16. The emission driver according to claim 15 , wherein:
the first and second input terminals of a k-th (k is an odd number) one of the stages are configured to receive the first and second clock signals, respectively; and
the first and second input terminals of a (k+1)-th one of the stages are configured to receive the second and first clock signals, respectively.
17. The emission driver according to claim 15 , wherein
the fourth transistor is coupled between the first power source and the first output terminal, the gate electrode of the fourth transistor being coupled to the first node,
the fifth transistor is coupled between the first output terminal and the second power source, the gate electrode of the fifth transistor being coupled to the second node, and
the output unit further comprises a second capacitor coupled between the first power source and the first output terminal.
18. The emission driver according to claim 15 , wherein the second driver comprises:
a sixth transistor coupled between the first power source and a second output terminal, and comprising a gate electrode coupled to the first output terminal;
a seventh transistor coupled between the second output terminal and the second input terminal, and comprising a gate electrode coupled to a third node;
an eighth transistor coupled between the third node and the bidirectional driver, and comprising a gate electrode coupled to the first input terminal; and
a third capacitor coupled between the third node and the second output terminal.
19. The emission driver according to claim 15 , further comprising an eleventh transistor coupled between the first node and the second power source, and comprising a gate electrode configured to receive a reset signal.
20. The emission driver according to claim 19 , wherein the reset signal is configured to be supplied at least once when power is turned on or off.
21. The emission driver according to claim 15 , further comprising a twelfth transistor coupled between the first capacitor and the second input terminal, and comprising a gate electrode coupled to the second node.