Semiconductor light emitting device

1. A semiconductor light emitting device comprising:

an n-type semiconductor layer containing a nitride semiconductor;

a p-type semiconductor layer containing a nitride semiconductor; and

a light emitting layer provided between the n-type semiconductor layer and the p-type semiconductor layer, the light emitting layer including a plurality of barrier layers and a plurality of well layers, being alternately stacked,

a p-side barrier layer being closest to the p-type semiconductor layer among the plurality of barrier layers, the p-side barrier layer including a first and a second layer, the first layer containing group III elements, the second layer being stacked with the first layer, and the second layer containing group III elements,

an In composition ratio in the group III elements of the second layer being higher than an In composition ratio in the group III elements of the first layer, or the first layer not containing In and the second layer containing In, and

an average In composition ratio of the p-side barrier layer being higher than an average In composition ratio of an n-side barrier layer being closest to the n-type semiconductor layer among the plurality of barrier layers.

2. The device according to claim 1 , wherein

a thickness of the first layer is less than 3 nanometers, and

a thickness of the second layer is not more than 2 nanometers.

3. The device according to claim 1 , wherein

the plurality of barrier layers includes an intermediate barrier layer between the p-side barrier layer and the n-side barrier layer, and

the intermediate barrier layer includes

a third layer containing group III elements, and

a fourth layer being stacked with the third layer and containing group III elements, an In composition ratio in the group III elements of the fourth layer being higher than an In composition ratio in the group III elements of the third layer, and

an average In composition ratio of the intermediate barrier layer is lower than the average In composition ratio of the p-side barrier layer and is higher than the average In composition ratio of the n-side barrier layer.

4. The device according to claim 1 , wherein

the In composition ratio of the first layer is not more than 0.02, and

the In composition ratio of the second layer is not more than 0.13.

5. The device according to claim 1 , wherein

the In composition ratio of the first layer is 0.00, and

the In composition ratio of the second layer is not less than 0.08.

6. The device according to claim 3 , wherein

the In composition ratio of the third layer is not more than 0.02, and

the In composition ratio of the fourth layer is not more than 0.13.

7. The device according to claim 3 , wherein

the In composition ratio of the third layer is 0.00, and

the In composition ratio of the fourth layer is not less than 0.08.

8. The device according to claim 1 , wherein the In composition ratio of the second layer is not more than half of the In composition ratio of a p-side well layer being closest to the p-type semiconductor layer of the plurality of well layers.

9. The device according to claim 1 , wherein

a thickness of a p-side well layer being closest to the p-type semiconductor layer of the plurality of well layers is larger than a thickness of a n-side well layer being closest to the n-type semiconductor layer of the plurality of well layers.

10. The device according to claim 1 , wherein

a thickness of each of the plurality of barrier layers is not more than 10 nanometers, and

a thickness of each of the plurality of well layers is not less than 3 nanometers and not more than 6 nanometers.

11. The device according to claim 1 , wherein a band gap energy of the second layer is smaller than a band gap energy of the first layer.

12. The device according to claim 1 , wherein the first layer and the second layer are included in a plurality in the p-side barrier layer, the first layer and the second layer being alternately stacked.

13. The device according to claim 3 , further including the intermediate barrier layer in a plurality, the third layer and the fourth layer being provided in each of the plurality of intermediate barrier layers.

14. The device according to claim 3 , wherein the third layer and the fourth layer are included in a plurality in the intermediate barrier layer, the third layer and the fourth layer being alternately stacked.

15. The device according to claim 3 , wherein

a thickness of the third layer is less than 3 nanometers, and

a thickness of the fourth layer is not more than 2 nanometers.

16. The device according to claim 3 , wherein an average In composition ratio of the intermediate barrier layer decreases in a stepwise fashion from the intermediate barrier layer close to the p-type semiconductor layer toward the intermediate barrier layer close to the n-type semiconductor layer.

17. The device according to claim 1 , wherein an average In composition ratio of the intermediate barrier layer is larger as the intermediate barrier layer is closer to the p-type semiconductor layer, and is smaller as the intermediate barrier layer is closer to the n-type semiconductor layer.

18. The device according to claim 12 , wherein each of the In composition ratios of the plurality of second layers is larger as the second layers are closer to the p-type semiconductor layer, and is smaller as the second layers are closer to the n-type semiconductor layer.

19. The device according to claim 1 , wherein

the plurality of barrier layers is provided in at least one additional plurality, such that when an adjacent plurality of the barrier layers are set to one pair and the pair is configured in a plurality, the adjacent plurality of the barrier layers have one common average In composition ratio in the one pair.

20. The device according to claim 19 , wherein the average In composition ratio of the adjacent plurality of the barrier layers in the one pair decreases in a stepwise fashion from the p-type semiconductor layer toward the n-type semiconductor layer.