Nitride semiconductor wafer including different lattice constants

1. A nitride semiconductor wafer comprising:

a silicon substrate having a major surface;

a lower strain relaxation layer provided on the major surface and including a nitride semiconductor, the lower strain relaxation layer having a first lattice constant;

an intermediate layer provided on the lower strain relaxation layer and including a nitride semiconductor;

an upper strain relaxation layer provided on the intermediate layer and including a nitride semiconductor; and

a functional layer provided on the upper strain relaxation layer and including a nitride semiconductor, the intermediate layer including:

a first lower layer provided on the lower strain relaxation layer and including a nitride semiconductor, the first lower layer having a second lattice constant larger than the first lattice constant;

a first doped layer provided on the first lower layer and including a nitride semiconductor, the first doped layer having a third lattice constant larger than the second lattice constant and containing an impurity at a concentration of 1×10 18 cm −3 or more and less than 1×10 21 cm −3 ; and

a first upper layer provided on the first doped layer and including a nitride semiconductor, the first upper layer having a fourth lattice constant larger than the third lattice constant and larger than the second lattice constant.

2. The wafer according to claim 1 , wherein

a composition ratio of the first doped layer is different from a composition ratio of the first lower layer, and also different from a composition ratio of the first upper layer.

3. The wafer according to claim 1 , wherein the impurity includes at least one of silicon (Si), magnesium (Mg), manganese (Mn), iron (Fe), oxygen (O), and carbon (C).

4. The wafer according to claim 1 , wherein the intermediate layer further includes:

a second lower layer provided on the first upper layer and including a nitride semiconductor, the second lower layer having a fifth lattice constant smaller than the fourth lattice constant;

a second doped layer provided on the second lower layer and including a nitride semiconductor, the second doped layer having a sixth lattice constant larger than or equal to the fifth lattice constant and containing an impurity at a concentration of 1×10 18 cm −3 or more and less than 1×10 21 cm −3 ; and

a second upper layer provided on the second doped layer and including a nitride semiconductor, the second upper layer having a seventh lattice constant larger than or equal to the sixth lattice constant and larger than the fifth lattice constant.

5. The wafer according to claim 4 , wherein the intermediate layer further includes a second strain relaxation layer provided between the first upper layer and the second lower layer and including a nitride semiconductor, the second strain relaxation layer having a eighth lattice constant smaller than the fifth lattice constant.

6. The wafer according to claim 5 , wherein the second strain relaxation layer is Al z2 Ga 1-z2 N (0<z 2 ≦1).

7. The wafer according to claim 4 , wherein

the second lower layer includes Al xa2 In ya2 Ga 1-xa2-ya2 N (0≦xa 2 ≦1, 0≦ya 2 <1, xa 2 +ya 2 ≦1),

the second doped layer includes Al xb2 In yb2 Ga 1-xb2-yb2 N (0≦xb 2 <xa 2 , ya 2 ≦yb 2 <1, xb 2 +yb 2 ≦1), and

the second upper layer includes Al xc2 In yc2 Ga 1-xc2-yc2 N (0≦xc 2 <xb 2 , yb 2 ≦yc 2 <1, xc 2 +yc 2 ≦1).

8. The wafer according to claim 1 , wherein

the first lower layer includes Al xa1 Ga 1-xa1 N (0<xa 1 ≦1),

the first doped layer includes Al xb1 Ga 1-xb1 N (0<xb 1 <xa 1 ), and

the first upper layer includes Al xc1 Ga 1-xc1 N (0≦xc 1 <xb 1 ).

9. The wafer according to claim 1 , wherein

the lower strain relaxation layer is AlN.

10. The wafer according to claim 1 , wherein

the upper strain relaxation layer is Al z0 Ga 1-z0 N (0<z 0 ≦1).

11. The wafer according to claim 1 , wherein

a thickness of the first doped layer is 20 nanometers or more and 150 nanometers or less.

12. The wafer according to claim 1 , wherein

a thickness of the first lower layer is 100 nanometers or more and 500 nanometers or less.

13. The wafer according to claim 1 , wherein

a thickness of the first upper layer is 100 nanometers or more and 500 nanometers or less.

14. The wafer according to claim 1 , wherein

a first density of dislocations extending in a direction from the first lower layer toward the first upper layer in the functional layer is lower than a second density of dislocations extending in the direction in the first lower layer.

15. The wafer according to claim 1 , wherein

the first lower layer includes Al xa1 In ya1 Ga 1-xa1-ya1 N (0≦xa 1 <1, 0≦ya 1 <1),

the first doped layer includes Al xb1 In yb1 Ga 1-xb1-yb1 N (0≦xb 1 <1, 0≦yb 1 <1),

the first upper layer includes Al xc1 In yc1 Ga 1-xcl-yc1 N (0≦xc 1 <1, 0≦yc 1 <1),

the xa 1 is different from the xb 1 and different from the xc 1 the xb 1 is different from the xc 1 , and

the ya 1 is different from the yb 1 and different from the yc 1 , the yb 1 is different from the yc 1 .

16. The wafer according to claim 1 , wherein

the first lower layer includes Al xa1 In ya1 Ga 1-xa1-ya1 N (0<xa 1 <1, 0≦ya 1 <1, xa 1 +ya 1 ≦1),

the first doped layer includes Al xb1 In yb1 Ga 1-xb1-yb1 N (0≦xb 1 <1, 0≦yb 1 <1, xb 1 +yb 1 ≦1

the first upper layer includes Al xc1 In yc1 Ga 1-xc1-yc1 N (0≦xc 1 <1, 0≦yc 1 <1, xc 1 +yc 1 ≦1),

the xa 1 is different from the xb 1 and different from the xc 1 , the xb 1 is different from the xc 1 ,and

the ya 1 is different from the yb 1 and different from the yc 1 the yb 1 is different from the yc 1 .

17. The wafer according to claim 1 , wherein

the first lower layer includes Al xa1 Ga 1-xa1 N (0<xa 1 ≦1),

the first doped layer includes Al xb1 Ga 1-xb1 N (0<xb 1 <xa1), and

the first upper layer includes Al xc1 Ga 1-xc1 N (0≦xc 1 <xb1).