System and method for peripheral device communications

1. A method for operating a host device, the method comprising:

comparing, by a direct memory access module, a predetermined response of a peripheral device to a response token received from the peripheral device, wherein the predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device;

controlling, by the direct memory access module and without interrupting a host control module, a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token; and

selectively passing, by an interrupt control module in communication with the direct memory access module, interrupts to the host control module when the predetermined response does not match the response token.

2. The method of claim 1 , further comprising:

storing the predetermined response in a first array;

storing the response token in a first register; and

comparing contents of the first array to contents of the first register.

3. The method of claim 1 , further comprising:

storing the response token in a first register associated with the peripheral control module;

receiving, at the first register, the first data from the first memory;

receiving, at the host control module, second data from the first memory; and

storing, in a first array of a second memory, the predetermined response.

4. The method of claim 3 , wherein the first data includes overhead data and the second data includes payload data.

5. The method of claim 3 , further comprising controlling a transfer of the second data in response to the interrupts.

6. The method of claim 3 , further comprising:

defining a source memory address in the first memory;

defining a destination memory address in the second memory; and

defining sizes of the first data and the second data.

7. The method of claim 1 , further comprising processing a secure digital input and output header to run an interrupt header sequence without interrupting the host control module until the interrupt header sequence is complete.

8. The method of claim 1 , further comprising transferring the first data from the first memory to the peripheral control module when the predetermined response matches the response token.

9. The method of claim 1 , further comprising:

passing the interrupts when the predetermined response does not match the response token; and

not passing the interrupts when the predetermined response matches the response token.

10. The method of claim 1 , further comprising:

communicating via packets with the peripheral device, wherein the packets include interrupt header portions and payload portions;

initiating predetermined secure digital command-response sequences based on the interrupt header portions without interrupting the host control module until the predetermined secure digital command-response sequences are complete;

based on the predetermined secure digital command-response sequences, transmitting commands to and receiving responses from the peripheral device; and

interrupting the host control module subsequent to the peripheral device responding to the commands.

11. The method of claim 10 , wherein:

the command-response sequences include a plurality of descriptors identifying locations in the first memory for the commands;

the commands are standard secure digital input and output commands; and

the method further comprises accessing the commands based on the descriptors.

12. The method of claim 11 , further comprising providing communication between the host control module and the peripheral device using a secure digital control module.

13. The method of claim 1 , wherein the peripheral device comprises at least one of a secure digital card, a secure digital input and output card, and a multi-media control card.

14. The method of claim 13 , wherein the secure digital input and output card comprises a radio frequency transceiver module connected to an antenna.

15. The method of claim 1 , wherein:

the transfer of the first data comprises a transfer of a block of data from the first memory to a first register of the peripheral control module; and

the peripheral device is located remotely from the host device.

16. The method of claim 15 , further comprising communicating with the host device via a secure digital input and output interface.

17. The method of claim 15 , further comprising:

providing instructions to access a first array of a second memory and a second array of the second memory;

storing a sequence of expected responses, received from the peripheral device, in the first array; and

storing a sequence of commands, to be executed by the peripheral device, in the second array, wherein the sequence of commands includes the first command.

18. The method of claim 17 , further comprising:

triggering an interrupt when the peripheral device has data to be transmitted to the host device; and

servicing the interrupt, triggered by the peripheral device, by copying the first command in the second array to a second register in the peripheral control module.

19. The method of claim 18 , further comprising:

sending the response token to the first register; and

triggering an interrupt in response to the response token.

20. The method of claim 18 , further comprising:

receiving packets in chunks of predetermined size, wherein the packets include the first data and second data, wherein the first data includes overhead data, and wherein the second data includes payload data; and

determining a length of the packets based on a number of data chunks transmitted from the peripheral device, wherein a last one of the sequence of commands identifies the length.

21. The method of claim 1 , further comprising processing a secure digital input and output header to run an interrupt header sequence without interrupting the host control module until the interrupt header sequence is complete.