IP Library Granted Patent US 8,742,509
Granted Patent B2
US 8,742,509 · App. 13/410,073 · Granted Jun 3, 2014

Apparatus and method for FinFETs

Inventors: Yi-Jing Lee (Hsin-Chu, TW); You-Ru Lin (New Taipei, TW); Cheng-Tien Wan (Tainan, TW); Cheng-Hsien Wu (Hsin-Chu, TW); Chih-Hsin Ko (Fongshan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,742,509
App. No.
13/410,073
Granted
Jun 3, 2014
Kind
B2
Abstract

A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

Claims (39)

1. An apparatus comprising:

a first isolation region formed in a substrate, wherein the first isolation region has a first non-vertical sidewall;

a second isolation region formed in the substrate, wherein the second isolation region has a second non-vertical sidewall;

a V-shaped groove formed in the substrate, wherein the V-shaped groove, the first non-vertical sidewall and the second non-vertical sidewall form a cloak-shaped recess in the substrate;

a cloak-shaped active region formed in the cloak-shaped recess over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region, a first triangular region embedded in the first isolation region, a second triangular region embedded in the second isolation region and a V-shaped bottom portion, and wherein the cloak-shaped active region comprises:

a first drain/source region;

a second drain/source region; and

a channel between the first drain/source region and the second drain/source region; and

a gate electrode wrapping the channel of the cloak-shaped active region.

2. The apparatus of claim 1 , further comprising:

a gate dielectric layer formed between the cloak-shaped active region and the gate electrode.

3. The apparatus of claim 1 , wherein the cloak-shaped active region is formed of silicon germanium.

4. The apparatus of claim 1 , wherein a turning point angle formed by the first non-vertical sidewall and the V-shaped groove is a range from about 130 degrees to about 160 degrees.

5. The apparatus of claim 1 , wherein the first isolation region is a shallow trench isolation structure.

6. The apparatus of claim 1 , wherein the V-shaped groove has an interior angle in a range from about 100 degrees to about 110 degrees.

7. The apparatus of claim 1 , wherein the gate electrode, the first drain/source region, the second drain/source region and the channel form a FinFET.

8. A device comprising:

a first drain/source region formed in a substrate;

a second drain/source region formed in the substrate;

a channel between the first drain/source region and the second drain/source region, wherein the first drain/source region, the second drain/source region and the channel form a cloak-shaped active region, wherein the cloak-shaped active region has a V-shaped bottom and wherein a first triangular region of the cloak-shaped active region is embedded in a first isolation region and a second triangular region of the cloak-shaped active region is embedded in a second isolation region; and

a gate electrode wrapping the channel.

9. The device of claim 8 , wherein the V-shaped bottom has an interior angle in a range from about 100 degrees to about 110 degrees.

10. The device of claim 8 , further comprising:

a first isolation region formed in the substrate;

a second isolation region formed in the substrate, wherein the first isolation region and the second isolation region are formed on opposite sides of the cloak-shaped active region; and

a gate dielectric layer formed between the gate electrode and the cloak-shaped active region.

11. The device of claim 10 , wherein the gate dielectric layer comprises:

a first portion formed between the first isolation region and the gate electrode;

a second portion formed between a first sidewall of the cloak-shaped active region and the gate electrode;

a third portion formed between a top surface of the cloak-shaped active region and the gate electrode;

a fourth portion formed between a second sidewall of the cloak-shaped active region and the gate electrode; and

a fifth portion formed between the second isolation region and the gate electrode.

12. The device of claim 10 , wherein:

the first isolation region comprises a shallow trench isolation structure; and

the second isolation region comprises the shallow trench isolation structure.

13. The device of claim 8 , wherein:

the first drain/source region is formed of silicon germanium;

the second drain/source region is formed of silicon germanium; and

the channel is formed of silicon germanium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2012
From: LEE, YI-JING; LIN, YOU-RU; WAN, CHENG-TIEN; WU, CHENG-HSIEN; KO, CHIH-HSIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 027792/0660 →
Continuity (1)
Related Publication 20130228875A1 · Sep 5, 2013