Energy efficient microprocessor platform based on instructional level parallelism
Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.
1. A processing architecture comprising:
a fetch unit configured to fetch an input stream of instructional data, the instructional data comprising instructions; and
a scheduler to receive the stream of instructional data from the fetch unit, the scheduler configured to create a schedule for processing the instructions from the stream of instructional data and allocate the instructions and schedule for processing the instructions among a plurality of computational units, wherein the scheduler is configured to adjust voltage and frequency settings of the processing architecture, and wherein each of the plurality of computational units comprise:
a control unit coupled to the scheduler, the control unit being configured to receive and decode the instructions into decoded data; and
an execution unit coupled to a corresponding control unit, the execution unit being configured to receive and execute the decoded data.
2. The processing architecture of claim 1 , further comprising a register file, the register file configured to store the decoded and executed data from the plurality of computational units.
3. The processing architecture of claim 2 , wherein the register file is a common file shared by each of the execution units, and wherein the register file is configured to store the decoded and executed data and make the decoded and executed data accessible to each of the execution units.
4. The processing architecture of claim 1 , wherein the scheduler is configured to optimize the throughput and power consumption of the processing architecture by instructing the processor to adjust the voltage and frequency of the processing architecture.
5. The processing architecture of claim 1 , wherein the scheduler is configured to instruct the processing architecture to operate in a low power mode, reducing voltage and frequency of the processing architecture based on the utilization of the plurality of computational units.
6. The processing architecture of claim 1 , wherein the scheduler is configured to instruct the processing architecture to operate in a high power mode, increasing voltage and frequency of the processing architecture based on the utilization of the plurality of computational units.
7. The processing architecture of claim 1 , wherein the scheduler is configured to instruct the processing architecture to operate in a high power mode, increasing the voltage and frequency of the processing architecture to achieve a higher throughput of the processing architecture.
8. The processing architecture of claim 1 , wherein the fetch unit is configured to fetch up to four instructions at a time.
9. The processing architecture of claim 1 , wherein the scheduler is configured to schedule the instructions to be executed by the execution units without changing the order of instructions within the stream of instructional data.