Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device having a 6F 2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern ( 14 x ) linearly extending in a first direction and a second support pattern ( 14 y ) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.
1. A semiconductor device comprising:
a plurality of memory cells having a plurality of capacitors, the plurality of capacitors being divided into a first group and a second group, each of the capacitors being located at an intersection of a corresponding one of first parallel lines and a corresponding one of second parallel lines, and the plurality of capacitors including a plurality of lower electrodes; and
a support film formed to hold the plurality of lower electrodes, and to include a plurality of openings,
wherein each of the capacitors belonging to the first group contacts an entire circumference of an outer side face of the lower electrode thereof to the support film, and
wherein each of the capacitors belonging to the second group does not contact an entire circumference of an outer side face of the lower electrode thereof to the support film so that the support film uncovers the entire circumference of the outer side face of the lower electrode of each of the capacitors belonging to the second group by a corresponding one of the plurality of openings of the support film.
2. The semiconductor device according to claim 1 , wherein the lower electrode is continuously supported by the support film with 1/3 or more of the entire circumference of the outer side face thereof.
3. The semiconductor device according to claim 1 , wherein the support film is arranged so as to come into contact with at least a portion of upper-end outer side face of the lower electrodes.
4. The semiconductor device according to claim 1 , wherein the support film contacts to the lower electrodes at a level without an upper-end level of the lower electrodes.
5. The semiconductor device as claimed in claim 1 ,
wherein a width of the support film in a first direction positioned between first and second openings placed adjacently among the plurality of openings is larger than a width of the support film in a second direction positioned between third and fourth openings placed adjacently among the plurality of openings, the second direction being perpendicular to the first direction.
6. The semiconductor device according to claim 1 ,
wherein the support film includes a pattern combining a first support pattern linearly extending in a first direction and a second support pattern linearly extending in a second direction that intersects the first direction, and
wherein the lower electrode of each of the capacitors belonging to the first group is arranged at an intersection of the first and the second support patterns.
7. The semiconductor device according to claim 6 ,
wherein the intersection of the first and the second support patterns includes one or two capacitors belonging to the first group.
8. A semiconductor device comprising:
a plurality of capacitors formed over a semiconductor substrate, the plurality of capacitors including a plurality of lower electrodes, each of the plurality of lower electrodes being a cylindrical shape and divided into a first group and a second group; and
an insulating support film which supports the plurality of lower electrodes and includes a plurality of openings, the insulating support film contacting an entire circumference of an outer wall of each of the plurality of lower electrodes belonging to the first group, the insulating support film contacting a partial circumference of an outer wall of each of the plurality of lower electrodes belonging to the second group so that a part of the outer wall of each of the plurality of lower electrodes belonging to the second group is positioned within a portion of a corresponding one of the plurality of openings.
9. The semiconductor device according to claim 8 , further comprising:
an additional insulating film provided over the semiconductor substrate and contacting a bottom of each of the plurality of lower electrodes,
wherein the insulating support film contacts the plurality of lower electrodes at a portion other than the bottom of each of the plurality of lower electrodes.
10. The semiconductor device according to claim 9 ,
wherein the portion other than the bottom is a top portion of each of the plurality of lower electrodes.
11. The semiconductor device as claimed in claim 8 ,
wherein the plurality of lower electrodes of the first group are arranged on a line in a first direction.
12. The semiconductor device as claimed in claim 11 ,
wherein the plurality of lower electrodes of the first group are further arranged on a line in a second direction different from the first direction.
13. The semiconductor device as claimed in claim 12 ,
wherein the first direction is perpendicular to the second direction.
14. The semiconductor device as claimed in claim 11 ,
wherein none of the plurality of lower electrodes of the first group are arranged on a line in a second direction perpendicular to the first direction.
15. The semiconductor device as claimed in claim 8 ,
wherein a width of the insulating support film in a first direction positioned between first and second openings placed adjacently among the plurality of openings is larger than a width of the insulating support film in a second direction positioned between third and fourth openings placed adjacently among the plurality of openings, the second direction being perpendicular to the first direction.
16. The semiconductor device as claimed in claim 8 ,
wherein first to fourth lower electrodes among the plurality of lower electrodes are arranged to place at a corner of a square pattern view from the top of the semiconductor device so that the first and second lower electrodes are placed on a first diagonal line of the square pattern and the third and fourth lower electrodes are placed on a second diagonal line of the square pattern, and
wherein a corresponding one of the plurality of openings includes an edge extending between the first and second lower electrodes.
17. The semiconductor device according to claim 8 ,
wherein each of the plurality of lower electrodes is located at an intersection of a corresponding one of first parallel lines comprising more than three lines and a corresponding one of second parallel lines comprising more than three lines.
18. The semiconductor device according to claim 17 ,
wherein the plurality of openings are substantially same in shape, and are arranged on a line in a first direction and further arranged on a line in a second direction different from the first direction.
19. The semiconductor device according to claim 18 ,
wherein the first direction is perpendicular to the second direction.
20. The semiconductor device according to claim 18 ,
wherein each of the plurality of openings includes a substantially quadrangular shape view from the top of the semiconductor device, and
wherein the quadrangular shape includes two opposed sides longer than the other two opposed sides.
21. The semiconductor device according to claim 18 ,
wherein each of the plurality of openings is associated with five or six lower electrodes belonging to the second group.
22. The semiconductor device according to claim 20 ,
wherein the plurality of lower electrodes belonging to the first group are located between two openings faced in adjacent shorter sides thereof, and along two lines parallel to the adjacent shorter sides, and
wherein each one of the lower electrodes belonging to the first group is arranged on an extension of each longer side of the opening.
23. The semiconductor device according to claim 20 ,
wherein the plurality of lower electrodes belonging to the first group are located between two openings faced in adjacent shorter sides thereof, and along one line parallel to the adjacent shorter sides, and
wherein each one of the lower electrodes belonging to the first group is arranged on an extension of either longer side of the opening.
24. The semiconductor device according to claim 22 ,
wherein each of the plurality of openings is associated with five or six lower electrodes belonging to the second group.
25. The semiconductor device according to claim 23 ,
wherein each of the plurality of openings is associated with five or six lower electrodes belonging to the second group.