Apparatuses and methods for encoding using error protection codes
Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.
1. An electronically-implemented method of protecting program data, the method comprising:
retrieving coefficient data for computation of an error protection code using a canonical form, the computed coefficient data representing coefficients employed to compute parity data from program data, wherein the coefficient data is independent of program data;
combining the coefficient data and the program data to compute an error protection code comprising parity data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and
storing the program data and the error protection code in memory.
2. The method of claim 1 , wherein storing the coefficient data for the error protection code in memory comprises storing in a memory device of a computing system.
3. The method of claim 1 , further comprising computing or retrieving the coefficient data responsive to a selection of the error protection code.
4. The method of claim 3 , wherein computing or retrieving responsive to the selection of the error protection code comprises computing responsive to the selection of the error protection code by a user.
5. The method of claim 1 , further comprising using the stored program data and the stored parity data to correct one or more errors in the stored program data.
6. The method of claim 1 , further comprising computing the parity data in parallel.
7. The method of claim 1 , further comprising using the computed coefficient data to compute respective parity data for different sets of program data stored in different memory arrays.
8. The method of claim 1 , wherein the computed coefficient data is stored in a look-up table.
9. The method of claim 1 , wherein the error protection code comprises a generalized block oriented algebraic error protection code.
10. The method of claim 9 , wherein the generalized block oriented algebraic error protection code comprises a BCH code or a Reed-Solomon code.
11. The method of claim 1 , wherein the canonical coefficients are based, at least in part, on a generator polynomial.
12. An apparatus comprising:
circuitry configured to compute parity data based, at least in part, on program data and on pre-computed coefficient data representing canonical coefficients for an error protection code, wherein the pre-computed coefficient data are determined independent of the program data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and
a memory array configured to store the parity and program data.
13. The apparatus of claim 12 , wherein the circuitry comprises circuitry configured to compute the parity data in parallel.
14. The apparatus of claim 12 , wherein the circuitry includes an encoder.
15. The apparatus of claim 12 , wherein the circuitry includes a decoder.
16. The apparatus of claim 12 , wherein the pre-computed coefficient data is stored in a look-up table included in the circuitry.
17. The apparatus of claim 16 , wherein the pre-computed coefficient data comprises coefficient data computed external to the apparatus.
18. The apparatus of claim 12 , wherein the circuitry comprises combinational logic circuitry.
19. The apparatus of claim 12 , wherein the error protection code comprises a selectable error protection code.
20. The apparatus of claim 19 , wherein the selectable error protection code comprises one of the following types: a BCH code or a Reed-Solomon code.
21. The apparatus of claim 12 , wherein the apparatus comprises at least one of the following: a memory device, a tablet computer, a desktop computer, a laptop computer, a workstation, a server device, a personal digital assistant, a mobile communication device, or any combination thereof.
22. An apparatus comprising:
parity computing circuit blocks configured to compute associated parity data for corresponding groups of program data, the circuit blocks configured to apply pre-computed coefficients to one or more groups of program data, wherein the pre-computed coefficients are determined independent of the program data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and
a memory array configured to store the parity and program data.
23. The apparatus of claim 22 , wherein the pre-computed coefficients are independent of the groups of program data.
24. The apparatus of claim 23 , wherein the parity computing circuit blocks are configured to operate in parallel.