Semiconductor memory device having a hierarchical bit line scheme

1. A semiconductor memory device, comprising:

a bit line connected to a memory cell; and

a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line,

wherein the sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

2. The device of claim 1 , wherein the sense amplifier comprises:

a first transistor having a gate connected to a precharge signal line, a drain connected to the bit line, and a source connected to a first voltage;

a second transistor having a gate connected to the bit line, a drain connected to the global bit line, and a source connected to a selective power supply line; and

a third transistor having a gate connected to a restoration signal line, a drain connected to the bit line, and a source connected to the global bit line.

3. The device of claim 2 , wherein the selective power supply line is driven to a second voltage during a precharge operation and driven to the first voltage during a sensing operation.

4. The device of claim 3 , wherein the first voltage is a ground voltage, and the second voltage is a power supply voltage.

5. The device of claim 1 , further comprising a parity cell connected to a word line of the memory cell.

6. The device of claim 5 , further comprising a parity sense amplifier connected to a bit line of the parity cell,

wherein the parity sense amplifier provides data that is complementary to data stored in the parity cell to a parity global bit line and provides the complementary data of the parity global bit line to the parity cell during the active operation of the memory cell.

7. The device of claim 6 , wherein the parity cell stores predetermined data during an operation of writing data in the memory cell.

8. The device of claim 7 , wherein the semiconductor memory device determines that the data stored in the memory cell is true data when the data stored in the parity cell is the predetermined data and determines that the data stored in the memory cell is the complementary data when the data stored in the parity cell is not the predetermined data.

9. A semiconductor memory device, comprising:

a plurality of sub-memory cell array blocks including a plurality of memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines;

a plurality of first sense amplifier blocks disposed between the sub-memory cell array blocks and including first sense amplifiers configured to drive voltage levels of global bit lines in response to voltage levels of the bit lines of respective sub-memory cell array blocks; and

at least one second sense amplifier block including second sense amplifiers configured to sense and amplify the voltage levels of the global bit lines disposed across the sub-memory cell array blocks and the first sense amplifier blocks,

wherein each of the first sense amplifiers provides data that is complementary to data stored in a respective memory cell to the global bit line of the memory cell and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

10. The device of claim 9 , wherein at least one of the sub-memory cell array blocks further includes a parity cell connected to each of the word lines of the memory cells of the sub-memory cell array.

11. The device of claim 10 , wherein at least one of the first sense amplifier blocks further includes a first parity sense amplifier connected to a parity bit line of the parity cells and the first sense amplifier block is configured to provide data that is complementary to data stored in a first parity cell of the parity cells to a parity global bit line and provide the complementary data of the parity global bit line to the first parity cell during an access operation of a first memory cell to which the first parity cell is connected, and

the second sense amplifier block further includes a second parity sense amplifier configured to sense and amplify the voltage levels of the parity global bit line disposed across the at least one sub-memory cell array block and the at least one first sense amplifier block.

12. The device of claim 11 , wherein the first parity cell stores preset data during an operation of writing data in the first memory cell.

13. The device of claim 12 , wherein the semiconductor device determines that the data stored in the first memory cell is true data when the data stored in the parity cell is the preset data, and determines that the data stored in the first memory cell is the complementary data when the data stored in the parity cell is not the preset data.

14. The device of claim 9 , wherein the global bit lines are divided into even global bit lines and odd global bit lines to drive the even global bit lines separately from the odd global bit lines.

15. The device of claim 14 , wherein at least one of the sub-memory cell array blocks further includes even parity cells connected to each of the word lines of first memory cells in the sub-memory cell array block and odd parity cells connected to each of the word lines of second memory cells in the sub-memory cell array block.

16. The device of claim 9 , wherein at least one of the first sense amplifiers comprises:

a first transistor having a gate connected to a precharge signal line, a drain connected to a first bit line of the bit lines, and a source connected to a first voltage;

a second transistor having a gate connected to the first bit line, a drain connected to a first global bit line of the global bit lines, and a source connected to a selective power supply line; and

a third transistor having a gate connected to a restoration signal line, a drain connected to the first bit line, and a source connected to the first global bit line.

17. The device of claim 9 , wherein at least one of the second sense amplifiers transmits data provided to a write data line to the global bit line to which the second sense amplifier is connected during a write operation and latches the voltage of the global bit line during a restoration operation.

18. The device of claim 9 , wherein at least one of the second sense amplifiers comprises:

a first transistor configured to transmit the voltage of the global bit line to which the second sense amplifier is connected to a first node in response to a first sensing signal;

a first inverter configured to receive the voltage from the first node and output an inverted voltage to a second node;

a second inverter configured to receive the voltage from the second node an output an inverted voltage to a third node; a second transistor configured to transmit the voltage of the third node to the global bit line in response to a second sensing signal;

a third transistor configured to connect the first node and a write data line in response to a write column selection signal; and

a fourth transistor configured to connect the second node and a read data line in response to a read column selection signal.

19. The device of claim 9 , further comprising a precharge unit configured to precharge a global bit line to which the precharge unit is connected in response to a precharge signal.

20. A semiconductor memory device, comprising:

a memory cell connected to a bit line and a word line, wherein the bit line is separated from a global bit line; and

a sense amplifier configured to change a voltage level of the global bit line in response to a change in a voltage level of the bit line when the word line is enabled,

wherein the sense amplifier comprises:

a first transistor having a gate connected to a precharge signal line, a drain connected to the bit line, and a source connected to a first voltage;

a second transistor having a gate connected to the bit line, a drain connected to the global bit line, and a source connected to a selective power supply line; and

a third transistor having a gate connected to a restoration signal line, a drain connected to the bit line, and a source connected to the global bit line.