Multiple page size memory management unit
View Patent ↗A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.
1. A method, comprising:
determining if a translation lookaside buffer data array stores a physical address associated with a first address based on a first tag portion of the first address, the first tag portion associated with a first page size, wherein the determining further comprises:
performing a first comparison between the first tag portion and a first entry of a translation lookaside buffer tag array, wherein the first entry is selected based upon a first index of the first address; and
indicating that the translation lookaside buffer data array includes first data when the first tag portion matches the first entry; and
concurrently determining if the translation lookaside buffer data array stores the physical address associated with the first address based on a second tag portion of the first address, the second tag portion associated with a second page size, wherein the determining further comprises:
performing a second comparison between the second tag portion and a second entry of the translation lookaside buffer tag array, wherein the second entry is selected based upon a second index of the first address; and
indicating that the translation lookaside buffer data array includes second data when the second tag matches the second entry.
2. The method of claim 1 , wherein indicating that the translation lookaside buffer data array includes the first data further comprises providing a first match indication and indicating that the translation lookaside buffer data array includes the second data further comprises providing a second match indication, and further comprising:
providing a first entry of the translation lookaside buffer data array based on the first index;
providing a second entry of the translation lookaside buffer data array based on the second index; and
selecting from the first entry and the second entry based on the first match indication and the second match indication.
3. The method of claim 2 wherein providing the first match indication comprises providing the second match indication based on first page size information associated with the second entry.
4. The method of claim 3 , wherein providing the second match indication comprises providing the second match indication based on second page size information associated with the second entry.
5. The method of claim 1 , wherein indicating that the translation lookaside buffer data array includes the first data further comprises providing a first match indication, and further comprising:
selecting an entry of the translation lookaside buffer data array based on the first match indication; and
providing the physical address from the selected entry of the translation lookaside buffer data array.
6. The method of claim 1 , wherein the translation lookaside buffer comprises a multi-port read content addressable memory.
7. A device comprising
a memory management unit adapted to concurrently perform N page translations for N different page sizes, the memory management unit comprising:
a translation lookaside buffer adapted to concurrently provide N entries based on the N different page sizes; and
a comparison module adapted to:
compare a first entry of the N entries with a tag from a received address, wherein the first entry is selected based upon a first one of the N page sizes; and
provide a first hit indication if the first entry matches the first tag.
8. The device of claim 7 , wherein the N entries are each provided by the translation lookaside buffer based on a corresponding different one of N index fields of the received address.
9. The device of claim 7 , wherein the memory management unit further comprises:
a translation lookaside buffer data array adapted to receive the first hit indication and to provide a physical address from an entry of the translation lookaside buffer data array in response to receiving the first hit indication.
10. The device of claim 7 , wherein:
the translation lookaside buffer is a set associative translation lookaside buffer; and
each way is adapted to concurrently provide N entries to the N comparison blocks.
11. The device of claim 7 , wherein the first entry includes information adapted to indicate that the first entry is associated with one of the N different page sizes.
12. The device of claim 11 , wherein each comparison block is further adapted to:
determine if the information in the first entry indicates that the first entry is associated with the first page size; and
provide the first hit indication in response to the determining that the first entry indicates that the first entry is associated with the first page size.